Verilog module Instantiation

[Altera_Forum]

Don't really know whether i should post this Q here or not. 

I'm a student using modelsimSE 6.1f.  actually this Q is more to verilog...not on fpga hardware issue  i was wondering,how can i control the input to an instantiated module?  e.g: module bin2bcdAdder(input1,input2,bcd); /* . . . */ full_adder fa1(input1,input2,SUM,carryOut); endmodule  the testbench generates 0000 to 1111 into the module bin2bcdAdder how can i control the input only from 0000 to 1001 can be passed to the instantiated module full_adder?  and i'm trully sorry if i post this Q in the wrong section, or altera forum is only allowing altera's hardware related Q

[Altera_Forum]

You basicaly need to add soething like this somewhere in your code 

 if (input == 1001) begin  input <= 4'b0; end  But I guess you have no clue where to add it right ? Well, I can not help you there, not without the code.

[Altera_Forum]

module bin2bcdAdder(input1,input2,bcd); input input1,input2; output bcd; wire S; wire input1,input2; /*without this line, i can't assign the input values to A1,B1 and compile the code*/ reg A1,B1; addminus4bit am4b(A1,B1,0,S,V,C); always @ (A,B) begin if(A>1001|B>1001) begin A1=4'b0; B1=4'b0; end else begin A1=input1; B1=input2; end /*some codes here*/ end endmodulewell,i tried using the always block... 

or is it useless to use the > comparison? do i need to do case for each bit from 0000 to 1001?

[Altera_Forum]

module bin2bcdAdder(input1,input2,bcd); input input1,input2; output bcd; wire S; wire input1,input2; /*without this line, i can't assign the input values to A1,B1 and compile the code*/ reg A1,B1; addminus4bit am4b(A1,B1,0,S,V,C); always @ (A,B) // without a clock input this will NEVER work begin if((A>4'b1001)|(B>4'b1001)) begin A1<=4'b0; // proper assigments B1<=4'b0; //proper assigments end else begin A1<=input1; // proper assigments B1<=input2; // proper assigments end /*some codes here*/ end endmodule

[Altera_Forum]

--- Quote Start ---  module bin2bcdAdder(input1,input2,bcd); input input1,input2; output bcd; wire S; wire input1,input2; /*without this line, i can't assign the input values to A1,B1 and compile the code*/ reg A1,B1; addminus4bit am4b(A1,B1,0,S,V,C); always @ (A,B) // without a clock input this will NEVER work begin if((A>4'b1001)|(B>4'b1001)) begin A1<=4'b0; // proper assigments B1<=4'b0; //proper assigments end else begin A1<=input1; // proper assigments B1<=input2; // proper assigments end /*some codes here*/ end endmodule  --- Quote End ---    not all always block needs a clock rite?may i know why do i need a clock pulse for this one?

[Altera_Forum]

btw,it's all working now...tq^^ 

added A1 and B1 to the output port to simulate it and it runs well without the clock generation

[Altera_Forum]

I am getting error while instantiating modules on condition with the default module. it is giving error if i instantiate default mode. 

the code is much similar to this:  module top(//parameters);  addition u0(//parameters passing); line 2 'ifdef(flag)  sum u1(//passing the parameters); 'else  subtract u2(//passing the parameters); 'endif endmodule  if the module addition-u0 is removed, then only code is working properly. but i need to operate before conditional execution. plz help me.:cry: