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JHaye4
New Contributor I
176 Views

What is the best way to generate a multi-port front end using the EMIF for a Cyclone 10 GX device?

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Using the old SDRAM controllers they had support for multiple ports to use the same memory controller. This IP is not available in Quartus Pro for Cyclone 10 as far as I can see, what is the best way to achieve this?

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sstrell
Honored Contributor II
105 Views

The multi-port front end is a hard memory controller feature of Cyclone V devices. Cyclone 10 GX simply doesn't have this hardware, so you wouldn't be able to do this. The memory architecture for Cyclone 10 GX is similar to Arria 10 so it is an Avalon slave interface which multiple Avalon masters could access.

 

#iwork4intel

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sstrell
Honored Contributor II
106 Views

The multi-port front end is a hard memory controller feature of Cyclone V devices. Cyclone 10 GX simply doesn't have this hardware, so you wouldn't be able to do this. The memory architecture for Cyclone 10 GX is similar to Arria 10 so it is an Avalon slave interface which multiple Avalon masters could access.

 

#iwork4intel

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JHaye4
New Contributor I
105 Views

Thank you very much, that makes sense.

NurAida_A_Intel
Employee
105 Views

TQ @sstrell​ 😊 Totally agree with your point !

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