The following is a asi_rx module i creat with MegaWizard.
The device i use is EP4CGX30F324.
Pin T1&T2 are asi input.
I set the asi_rx signal to T2,and set I/O standard as LVDS.
But i can't finish fit step.
The quartus error message is :
Error: I/O bank QL0 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank
I think I/O standard should be
LVDS.Am i wrong?
asi_in asi_rxins(
.rst(~grst),
.asi_rx(ASI_RX),
.rx_clk135(clk_135m),
.cal_blk_clk(CLK_27M),
.gxb_powerdown(1'B0),
.reconfig_clk(),
.reconfig_togxb(),
.rx_data(asi_rx_d),
.rx_ts_status(),
.rx_data_clk(asi_rx_clk),
.rx_data_valid(asi_rx_vld),
.reconfig_fromgxb());
