Why MegaWizard generates Verilog files for DDR2 HP Controller VHDL designs?

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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Why MegaWizard generates Verilog files for DDR2 HP Controller VHDL designs?

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Hello all,

I use the MegaWizard to generate a DDR2 HP Controller for my ArriaII GX design. I am using VHDL and my ModelSim license supports only VHDL.

The MegaWizard generate most of files .vhd and .vho (ok) and a wrapper .v which is ok too.

The problem is that for the ALTMEMPHY variation it generates only mctrl_phy_alt_mem_phy.v which, yes, I can compile but I can't simulate as a dual language license would be needed for ModelSim.

How can I get a, say, mctrl_phy_alt_mem_phy.vhd out of MegaWizard?

Or how is mctrl_phy_alt_mem_phy.v intended to be used for VHDL users like me?

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