I am using Cyclone V with Quartus 18.1. I have 2 data input groups, each with a clock and 8 data signals, all differential.
Here is a sample of the verilog for clock1 and one data bit.
diff_in tck1_i (
.datain ( CKO1P ),
.datain_b ( CKO1N ),
.dataout ( tck1 )
diff_in d10_i (
.datain ( D1P_0 ),
.datain_b ( D1N_0 ),
.dataout ( d10 )
For months this has been working OK, then suddenly only clock1 and data bits d10-d13 are mapped correctly after a compile, all other bits show 2 inputs with no output on the viewer. See attached picture. Any idea what is happening?
Found the answer. It seems that more than half my design was optimized away. I solved it by inserting (*noprune*) before the destination register definition of each input signal. I'm sure it was easier to route, however...
Perhaps, the design doesn't required that much of LVDS output? or it is not declared in Quartus with that much of bus width.
Sometimes Quartus will optimize that by removing the floating pin.
Anyway, i am glad that your design is working fine now.