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Valued Contributor III
1,227 Views

Why lpm_mult can not be synthesized?

Hello, everyone 

I recently have tried to use Lpm_Mult to accomplish a complex multiplication. 

But the Analysis & Synthesis part in the Compile Design can not be processed. 

There are two Errors:  

(1) Text Design File syntax error: Text Design File contains '(' where ASSERT, CONSTANT, DEFINE ,DESIGN, 

FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected 

(2) Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE ,DESIGN, 

FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected 

 

This problem has troubled me for quite a long time, please help me. Thanks a lot
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3 Replies
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Valued Contributor III
9 Views

For a helpful answer, minimal information about the implemented design are necessary.

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Valued Contributor III
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Ok, in the design, Algorithm, I want to accompolish a complex number multiplication. 

The real and imaginary parts of the complex number come from NumOneReg and NumTwoReg. 

When StartCacu gets high, the caculation starts. 

Then, four LpmMult entity accomplish four multiplication needed. 

After that comes two addition. 

In Quartus ii, when I tried the Analysis & Synthesis, the two syntax errors come out, which are 

(1) Text Design File syntax error: Text Design File contains '(' where ASSERT, CONSTANT, DEFINE ,DESIGN, 

FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected 

(2) Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE ,DESIGN, 

FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected  

 

Please give me some advices. Thank you 

Below is the code. 

 

 

entity Algorithm is  

port( 

-- input 

Clk : in std_logic; 

Reset : in std_logic; 

NumOneReg : in std_logic_vector(31 downto 0); 

NumTwoReg : in std_logic_vector(31 downto 0); 

StartCacu : in std_logic; 

-- output 

CacuReg : out std_logic_vector(31 downto 0); 

CacuDone : out std_logic 

); 

end entity; 

 

architecture Addition of Algorithm is  

type CacuState is (Idle, Load, Multi, AddAll,CacuEnd ); 

signal CacuFSM : CacuState; 

signal A_Real : std_logic_vector(7 downto 0); 

signal A_Imagine : std_logic_vector(7 downto 0); 

signal B_Real : std_logic_vector(7 downto 0); 

signal B_Imagine : std_logic_vector(7 downto 0); 

signal RealOne : std_logic_vector(15 downto 0); 

signal RealTwo : std_logic_vector(15 downto 0); 

signal ImagineOne : std_logic_vector(15 downto 0); 

signal ImagineTwo : std_logic_vector(15 downto 0); 

signal RealOneMid : std_logic_vector(15 downto 0); 

signal RealTwoMid : std_logic_vector(15 downto 0); 

signal ImagineOneMid : std_logic_vector(15 downto 0); 

signal ImagineTwoMid : std_logic_vector(15 downto 0); 

signal ResultReal : std_logic_vector(15 downto 0); 

signal ResultImagine : std_logic_vector(15 downto 0); 

signal EnMutiClk : std_logic; 

signal MultiCnt : integer; 

signal EnAddClk : std_logic; 

signal AddCnt : integer; 

constant MutiConstant : integer := 1; 

constant AddConstant : integer := 1; 

component LpmMult  

port 

clock : IN STD_LOGIC ; 

clken : IN STD_LOGIC ; 

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 

datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) 

);  

end component; 

component LpmAddSub 

port 

add_sub : IN STD_LOGIC ; 

clock : IN STD_LOGIC ; 

clken : IN STD_LOGIC ; 

dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) 

);  

end component; 

 

begin 

process(Reset, Clk) 

begin 

if Reset = '0'then 

CacuDone <= '0'; 

CacuReg <= (others => '0'); 

A_Real <= (others => '0'); 

A_Imagine <= (others => '0'); 

B_Real <= (others => '0'); 

RealOne <= (others => '0'); 

RealTwo <= (others => '0'); 

ImagineOne <= (others => '0'); 

ImagineTwo <= (others => '0'); 

CacuFSM <= Idle; 

EnMutiClk <= '0'; 

EnAddClk <= '0'; 

MultiCnt <= 0; 

AddCnt <= 0; 

elsif rising_edge(Clk)then 

CacuDone <= '0'; 

case CacuFSM is 

when Idle => 

if StartCacu = '1'then 

CacuFSM <= Load; 

end if;-- StartCacu 

EnMutiClk <= '0'; 

EnAddClk <= '0'; 

when Load =>  

A_Real <= NumOneReg(15 downto 8); 

A_Imagine <= NumOneReg(7 downto 0); 

B_Real <= NumTwoReg(15 downto 8); 

B_Imagine <= NumTwoReg(7 downto 0); 

EnMutiClk <= '1'; 

MultiCnt <= 0; 

AddCnt <= 0; 

CacuFSM <= Multi; 

when Multi =>  

if MultiCnt = MutiConstant then 

RealOne <= RealOneMid; 

RealTwo <= RealTwoMid; 

ImagineOne <= ImagineOneMid; 

ImagineTwo <= ImagineTwoMid; 

EnMutiClk <= '0'; 

EnAddClk <= '1'; 

MultiCnt <= 0; 

CacuFSM <= AddAll;  

else 

MultiCnt <= MultiCnt + 1; 

end if;  

when AddAll => 

if AddCnt = AddConstant then 

CacuReg(31 downto 16) <= ResultReal; 

CacuReg(15 downto 0) <= ResultImagine; 

AddCnt <= 0; 

EnAddClk <= '0'; 

CacuFSM <= CacuEnd; 

else 

AddCnt <= AddCnt + 1; 

end if; 

when CacuEnd => 

CacuDone <= '1'; 

CacuFSM <= Idle; 

when others => 

end case;  

end if; -- Reset 

end process; 

 

 

-- Multiplication 

A_Real_and_B_Real : LpmMult PORT MAP ( 

clock => Clk, 

clken => EnMutiClk, 

dataa => A_Real, 

datab => B_Real, 

result => RealOneMid 

); 

A_Imagine_and_B_Imagine : LpmMult PORT MAP ( 

clock => Clk, 

clken => EnMutiClk, 

dataa => A_Imagine, 

datab => B_Imagine, 

result => RealTwoMid 

); 

A_Real_and_B_Imagine : LpmMult PORT MAP ( 

clock => Clk, 

clken => EnMutiClk, 

dataa => A_Real, 

datab => B_Imagine, 

result => ImagineOneMid 

); 

A_Imagine_and_B_Real : LpmMult PORT MAP ( 

clock => Clk, 

clken => EnMutiClk, 

dataa => A_Imagine, 

datab => B_Real, 

result => ImagineTwoMid 

); 

 

-- Addition 

RealPart : LpmAddSub PORT MAP ( 

add_sub => '0', 

clock => Clk, 

clken => EnAddClk, 

dataa => RealOne, 

datab => RealTwo, 

result => ResultReal 

);  

ImaginePart : LpmAddSub PORT MAP ( 

add_sub => '1', 

clock => Clk, 

clken => EnAddClk, 

dataa => ImagineOne, 

datab => ImagineTwo, 

result => ResultImagine 

);  

end Addition;
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Valued Contributor III
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try first of all to correct your syntax errors at: 

if Reset = '0'then 

should be 

if Reset = '0' then 

 

and do the same for all others. I don't think it has any thing to do with your post title.
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