FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

FFT MegaCore Function Output is not as expected

PCIe HIP on Sandy Bridge E

AVALON-MM Master Template on DE2

Simulating custom DDR controller with ALTMEMPHY using ModelSim-Altera Starter edition

DSP Builder block for SD card

DSP Builder Advanced vs Mixed mode (Basic + Advanced)

Calculating Latency of DSP Builder System if Channel In and Out Blocks not used

ST FIFO question

DSP Builder not recognizing Fixed Point Toolbox License

Two Avalon ST Interfaces comparison

Hybrid Memory Cube HMC, IPs available ?

How interfacing HPC.II "local_signals" (ddr controller) with vhdl logic ?

Cyclone V GX implementation with 3 PCIe interfaces

100 MB Ethernet solution for Arria10

DDR2 synthesis error with Arria II Gx

Featured Content

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)