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Altera_Forum
Honored Contributor I
735 Views

Why won't my FIFO Fill?

Hello, 

 

In my SOPC design I have a Dual Clock FIFO fed by an SGDMA clocked at 80Mhz (no burst) and feeding a video pipeline clocked at 20Mhz. 

 

My SDRAM is 8bit and the SGDMA is clocking out 16bit (2 symbols per beat). 

 

The video sync generator implements backpressure with the 'ready' signal but yet the FIFO will not maintain a consistent level. 

 

Just entering a loop in my program which reads the FIFO CSR I get the following which is usual for what is continually repeated. 

(Each entry seperated by a few ms) 

 

It seems as if my FIFO isn't deep enough to successfully buffer the large amount of data that is passing through it (its ~8K deep but thats only 8 lines or so on my display), but at 80Mhz shouldnt my SGDMA be sourcing double what the video pipeline can sink, even without the backpressure from the video sync generator? 

 

FIFO Fill Level: 22 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 36 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 9 units. FIFO Fill Level: 2642 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 24 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 5 units. FIFO Fill Level: 30 units. FIFO Fill Level: 14 units. FIFO Fill Level: 0 units. FIFO Fill Level: 14 units. FIFO Fill Level: 24 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 40 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units. FIFO Fill Level: 0 units.  

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2 Replies
Altera_Forum
Honored Contributor I
33 Views

If you don't use bursts, it could require more clock cycles to fetch the data from the SDRAM, meaning that it won't be able to fill the FIFO at 40MB/s

Altera_Forum
Honored Contributor I
33 Views

Hello Daixiwen, 

 

Thank you very much thats got it! FIFO consistently full.
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