I referred Intel 5G LDPC FPGA IP user guide manual where i found in the LDPC decoder there are 384 bits of sink_data (IN_WIDTH = 6) at the input side for the LLRs data and 384 decoded bits for output. You states that 64 LLRs (means 384 bit data) is loaded at every clock cycle. For ASIC implementation, there should be 384 pins (64*6-bits for LLR) for at the input sides. Is it so?
As I understand it, you have some inquiries related to the 5G LDPC decoder and ASIC designing. Sorry as I am not familiar with ASIC design and could not really comment further on this. However, if I understand it correctly, generally this decoder will be data fed by other module ie module which convert the transmitted serial bit stream to LLR. In FPGA, the interconnect will be within FPGA.
Please let me know if there is any concern. Thank you.