FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6355 Discussions

a bug of switch?

Altera_Forum
Honored Contributor II
‎05-17-2010 08:17 AM
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Hi,  

I'm implementing a data path with a switch of VIP. 

From the VIP user guide, it mentioned that the status of switch can be read from its status register, when switch is running, it reads a 0 from bit0, otherwise it reads a 1, but in fact the status register is always read 0, no matter I stop or start the switch. 

I program in the way below. 

IOWR(ALT_VIP_SWI_0_BASE, 0x00, 0x00); 

tmp = IORD(ALT_VIP_SWI_0_BASE, 0x01); 

 

IOWR(ALT_VIP_SWI_0_BASE, 0x00, 0x01); 

tmp = IORD(ALT_VIP_SWI_0_BASE, 0x01); 

 

Thanks for reply!
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Altera_Forum
Honored Contributor II
‎05-17-2010 08:48 AM
297 Views

Hi, try  

tmp = IORD(ALT_VIP_SWI_0_BASE, 0x00);
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Altera_Forum
Honored Contributor II
‎05-17-2010 09:57 AM
297 Views

Hi, 

 

For the video IP cores "not running" usually means that this is a safe point to read and write your control registers. It is not directly related to what was written on the Go bit. The status register is most probably reading 0 because there is curently no data flowing through the switch.
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