a problems about using negative clk

[assn1]

The port definition is complete, but errors continue to occur.

always @(negedge clk_1Msec or negedge rst) begin
if(Control == 0) begin
if(rst == 0) begin
Msecs <= 0;
Mins <= 0;
Secs <= 0;
Hours <= 0;
Check <= 0;

This is it;

Error (10200): Verilog HDL Conditional Statement error at stopwatch.v(43): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

I couldn't find a grammatical error. I need help.

[ak6dn]

Well, that is not complete verilog. For one, it is missing three end statements corresponding to the begin statements.

posedge clk or negedge clk does not matter; neither will work as you wrote the verilog.

Then, the if (control == 0) begin statement uses a signal not in the sensitivity list (control) ...

... but embedded within that block is the if (rst == 0) begin statement which DOES use a signal in the sensitivity list (negedge rst).

That makes no semantic sense and does not translate to real logic.

So rewrite and repost a version of that always block that is meaningful, something like this ...

always @(negedge clk_1Msec or negedge rst)
    begin
    if (rst == 0)
        begin
        xxx <= 0;
        end
    else
        begin
        if (control == 0)
            begin
            xxx <= xxx + 1;
            end
        end
    end

And use the <code> block to make your code easily readable.

[assn1]

Thank you for your help. But I want to measure the laptime; to store the time-varying values where the clk jumps, I have to let it occur at the end of the cycle at the clk of the falling edge.

Here's the stopwatches module code. Could you please help me a little more?

<code>
module stopwatch(
clk_1Msec,
rst,
laptime,
Hours_L,
Mins_L,
Secs_L,
Msecs_L,
Start_S,
Stop_S,
rst_S,
Hours_S,
Mins_S,
Secs_S,
Msecs_S,
Control);

input clk_1Msec, rst, Start_S, Stop_S, rst_S, Control, laptime;
output [3:0] Hours_S;
output [5:0] Mins_S, Secs_S;
output [9:0] Msecs_S;

reg [9:0] Msecs;
reg [5:0] Mins, Secs;
reg [3:0] Hours;

reg [9:0] Msecs_L;
reg [5:0] Mins_L, Secs_L;
reg [3:0] Hours_L;

reg [1:0] Check;

assign Msecs_S = Msecs;
assign Secs_S = Secs;
assign Mins_S = Mins;
assign Hours_S = Hours;

always @(negedge clk or negedge rst) begin
if(Control == 0) begin
if(rst == 0) begin
Msecs <= 0;
Mins <= 0;
Secs <= 0;
Hours <= 0;
Check <= 0;

Msecs_L <= 0;
Mins_L <= 0;
Secs_L <= 0;
Hours_L <= 0;
end

if(laptime == 1) begin
Hours_L = Hours_S;
Mins_L = Mins_S;
Secs_L = Secs_S;
Msecs_L = Msecs_S;
end
end
end

always @(posedge clk or negedge rst) begin
if(Control == 0) begin
if(rst == 0) begin
Msecs <= 0;
Mins <= 0;
Secs <= 0;
Hours <= 0;
Check <= 0;

Msecs_L <= 0;
Mins_L <= 0;
Secs_L <= 0;
Hours_L <= 0;
end

else begin
if(Check + Stop_S > 0) begin
Msecs <= Msecs;
Mins <= Mins;
Secs <= Secs;
Hours <= Hours;
Check = 1;

if(rst_S == 1) begin
Msecs <= 0;
Mins <= 0;
Secs <= 0;
Hours <= 0;
Check <= 0;
end
end

if(!(Check + Stop_S)) begin
if(Stop_S == 1) begin
if(Hours == 12)
Hours = 0;

if(Mins == 60) begin
Hours = Hours + 1;
Mins = 0;
end

if(Secs == 60) begin
Mins = Mins + 1;
Secs = 0;
end

if(Msecs == 60) begin
Secs = Secs + 1;
Msecs = -1;
end

Msecs = Msecs + 1;
end

else begin
Msecs <= Msecs;
Mins <= Mins;
Secs <= Secs;
Hours <= Hours;
end
end
end
end
end

endmodule


[ak6dn]

The problem is your syntax for a register with an asynchronous reset is incorrect.

It must look like as follows:

always @(posedge clk or negedge rst)
    begin
    if (rst == 0)
        begin
        data <= 0;
        end
    else
        begin
        if (control)
            begin
            data <= data+1;
            end
        end
    end

in particular this syntax is INCORRECT:

always @(posedge clk or negedge rst)
    begin
    if (Control == 0)
        begin
        if (rst == 0)
            begin
    ...

If you want an async reset than the test on rst must come FIRST.

Otherwise remove the or negedge rst from the always sensitivity list and make it a synchronous reset block.

[assn1]

Thank you! It was very helpful.

[SyafieqS]

This seem a syntax issue on if else condition for Verilog. 

You need to check again the correct syntax.

[SyafieqS]

Let me know if there is any update or concern on this

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.