FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6356 Discussions

about timing problem of FIR II IP

Altera_Forum
Honored Contributor II
‎03-25-2016 05:11 AM
933 Views

Hi all, 

 

I want to use fir II IP , 4 channel data input the fir behind time-sharing , 

they share the same coefficient bank.  

But I don't know the correct input timing of fir?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.