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Valued Contributor III
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adding altera vip to existing qsys design

Hi everyone, 

 

I have a Cyclone V GX kit in addition to a Terasic 5 MP camera. I would like to add altera video and image processing ip's to the output of the camera, and view the effects on a computer monitor.  

 

The current output on the monitor from the camera is just a bunch of blurred lines when I add the 2d fir filter. Without it, the images from the camera appear as expected. 

 

So to clarify, what currently works is: Terasic Camera -> Frame Buffer -> Clocked Video output. 

 

What doesnt work is: Terasic Camera -> Frame Buffer -> Color Plane Sequencer -> 2D Fir Filter -> Color Plane Sequence (to convert sequential back to parallel) -> Clocked Video Output. 

 

Any help for resolving this would be greatly appreciated!
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Valued Contributor III
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How much filtering are you doing? If you have a the wrong coefficients for your filter you could easily get just a bunch of blurred lines. 

 

I would try the filter with minimal filtering first and see what you get. 

 

Pete
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Valued Contributor III
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--- Quote Start ---  

How much filtering are you doing? If you have a the wrong coefficients for your filter you could easily get just a bunch of blurred lines. 

 

I would try the filter with minimal filtering first and see what you get. 

 

Pete 

--- Quote End ---  

 

 

I just used the default coefficients that the IP generates. I can also add that the image size is 1280 (width) by 720 (height). Perhaps this is too large for the ip? 

 

At the moment this is what I'm using: http://www.alteraforum.com/forum/attachment.php?attachmentid=11059&stc=1
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Valued Contributor III
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Which clocks do you have inside your system? 

I expect you have 74.25 MHz (720p) for the input and if you don't change the resolution, also for the output?! 

So the Pixelclock is 74.25 MHz, but if you do not put the frequency up, you may loose information with your construction of CPS->FIR->CPS due to overflows/underflows. 

 

To achieve a better result (in a first stage) you could insert another FrameBuffer to decouple everything. (Of course your frame rate with updated frames will go down). 

 

So the pipeline could be: 

 

CVI -> FrameBuffer -> CPS ->FIR -> CPS -> FrameBuffer -> CVO 

 

The FrameBuffers should be configured with frame dropping and framerepetition. 

 

In order to test the (I think it should be) underflow at the output you could also insert a trace system with a vip-monitor and put the underflow-output to a dedicated LED. 

 

 

I hope this helps 

 

Regards
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Valued Contributor III
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Thank you for your recommendation Taz! I'm running my nios processor at 50 Mhz, and the camera + vip components + video output at the SDRAM controller clock speed of 125 Mhz, do you think that should be ok?

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Valued Contributor III
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If you decouple the input and the FIR with Framebuffers like I recommended for first tests, the frequencys should be okay. 

 

but if you have no decoupling around the FIR, this is not enough, it is an easy calculation: 

 

pixelclock for 720p is 74.25MHz, if you have for example RGB as colorspace, you will get 3 colorplanes per tick, if you try to process them in sequence you will need 3 times the pixelclock to be safe, which is quite to much for the whole pipeline. 

 

Regards
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