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Altera_Forum
Honored Contributor I
798 Views

Quartus DPRAM interface with Nios

I have defined a system with the following: 

- qsys system with Nios 

- tcl script to export avalon signals to the top module 

- two quartus DPRAM components - dpram0, dpram1 (external to Nios) 

- port a of dprams connected to avalon export (direct Nios write/read) 

- port b of dprams (read only) connected to other logic blocks 

 

My problem is that after Nios writes to port a of dpram0, port b of dpram0 is not updated with the written data until Nios writes to port a of dpram1 and vice-versa. 

Nios reads of port a indicate the correct data that was written. 

What am I missing?
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Altera_Forum
Honored Contributor I
68 Views

Problem solved. 

Nios writes to DPRAM were cached.
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