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altlvds_rx

XQSHEN
Novice
846 Views

How to make sure data is aligned with fclk when using altlvds_rx ip?

 

XQSHEN_0-1647873102472.png

 

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1 Solution
Ash_R_Intel
Employee
610 Views

Hi,

Please refer the ALTLVDS user guide section 1.3.2: https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/lvds-serdes-transmitter-receiver-ip-36681.html

 

In external PLL mode rx_coreclock can be used in the fabric logic to further process the data. In this mode, rx_coreclock is same as the rx_syncclock which is an input to the ALTLVDS_RX.

rx_syncclock is used to receive the parallel data.

 

Ash_R_Intel_0-1649998740563.png

 

Regards

 

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Ash_R_Intel
Employee
739 Views

Hi,

Can you please tell which device IP are you using?


Regards


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XQSHEN
Novice
730 Views
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Ash_R_Intel
Employee
664 Views

Hi,

The ALTLVDS IP has rx_coreclock signal. You can connect the fabric clock to it.


Regards


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XQSHEN
Novice
637 Views

where is this signal, rx_coreclock ?

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Ash_R_Intel
Employee
611 Views

Hi,

Please refer the ALTLVDS user guide section 1.3.2: https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/lvds-serdes-transmitter-receiver-ip-36681.html

 

In external PLL mode rx_coreclock can be used in the fabric logic to further process the data. In this mode, rx_coreclock is same as the rx_syncclock which is an input to the ALTLVDS_RX.

rx_syncclock is used to receive the parallel data.

 

Ash_R_Intel_0-1649998740563.png

 

Regards

 

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