FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

avalon multi-port SDRAM Controller

Altera_Forum
Honored Contributor II
‎09-16-2010 04:26 PM
1,083 Views

2 SDRAM 64Mb with 16-bit data  

 

The whenever the controller is access the data, can it turn off one SDRAM device completely with CLKE to save power while accessing the other. The SDRAM address arrangement is as follow: 

 

Row address : RA0 ~ RA12, 

Column address : (x16 : CA0 ~ CA9) 

 

Right now the microtronic SDRAM ip core has one CLK enable. How can configure the ip core such that it will know to turn the unused memory. I know chip select disable the unused functionally, but the sdram device still uses power with the clock enabled. 

 

-- Tom
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.