chained dma based design does not work when RC_64BITS_ADDR is enabled
chained dma based design does not work when RC_64BITS_ADDR is enabled in simulation or in FPGA, even when all addresses are 32-bit.
The same design works fine RC_64BITS_ADDR is disabled. SignalTap shows that read dma initiates read transaction as usual but it never receives reply. The suspicion is that the address of the transaction is not set correctly. Quartus version is 12.1sp1, Linux version is 2.6.32, FPGA is Arria V. Any info helping to understand/resolve this issue would be appreciated.