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Altera_Forum
Honored Contributor I
876 Views

clocked video input , output

Hi, 

In my design I try to simulate input video on fpga 

 

in the begin I connect test pattern to the output video and it work good 

then I generate test pattern and out with embbeded sync and connect it (out from qsys) 

to video input with embbede sync inside the qsys and output the signal to DVI monitor 

 

test pattern - > video out -> video input -> video out 

this link work good 

 

right now I try to connect the middle video out to video input but I change them to separate wire and the video don't work 

 

someone have an idea? 

here is the connection outside the qsys between input and output signals 

 

alt_vip_itc_4_clocked_video_vid_clk => clk_148_5mhz, 

alt_vip_itc_4_clocked_video_vid_data => ycbcr, 

-- alt_vip_itc_4_clocked_video_underflow => alt_vip_itc_4_clocked_video_underflow, 

alt_vip_itc_4_clocked_video_vid_datavalid => alt_vip_itc_4_clocked_video_vid_datavalid, 

alt_vip_itc_4_clocked_video_vid_v_sync => alt_vip_itc_4_clocked_video_vid_v_sync, 

alt_vip_itc_4_clocked_video_vid_h_sync => alt_vip_itc_4_clocked_video_vid_h_sync, 

-- alt_vip_itc_4_clocked_video_vid_f => alt_vip_itc_4_clocked_video_vid_f, 

 

alt_vip_cti_0_clocked_video_vid_clk => clk_148_5mhz, 

alt_vip_cti_0_clocked_video_vid_data => ycbcr, 

-- alt_vip_cti_0_clocked_video_overflow => alt_vip_itc_4_clocked_video_underflow, 

alt_vip_cti_0_clocked_video_vid_datavalid => alt_vip_itc_4_clocked_video_vid_datavalid, 

alt_vip_cti_0_clocked_video_vid_locked => alt_vip_cti_0_clocked_video_vid_locked, 

alt_vip_cti_0_clocked_video_vid_v_sync => alt_vip_itc_4_clocked_video_vid_v_sync, 

alt_vip_cti_0_clocked_video_vid_h_sync => alt_vip_itc_4_clocked_video_vid_h_sync, 

alt_vip_cti_0_clocked_video_vid_f => '0'
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Altera_Forum
Honored Contributor I
62 Views

inv the clock

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