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configure the triple speed ethernet register with verilog

Altera_Forum
Honored Contributor II
937 Views

Hello! I am using TSE(triple speed ethernet) ip core to implement communication bewteen my pc and the FPGA board(cyclone IV). But I don't know how to configure the TSE register with verilog. I do read some information from the user guide. For example, here are from the user guide: 

 

 

 

 

Base registers to configure the MAC function. At the minimum, you must 

configure the following functions: 

• Primary MAC address (mac_0/mac_1) 

• Enable transmit and receive paths (TX_ENA and RX_ENA bits in the 

command_config register) 

 

 

 

 

But I don't know how to realize this configuration in my quartus II project with verilog. 

Anything can be help! 

Best wishes!
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1 Reply
Altera_Forum
Honored Contributor II
125 Views

Hi, 

Register & Go through the “Implementing the Triple-Speed Ethernet MegaCore Function” training material for the detail stepwise solution, 

https://www.altera.com/support/training/course/otse1116p2.html 

 

Also, refer the design example & Intel FPGA Triple-Speed Ethernet IP Core User Guide & try at your end. 

 

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios... 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ethernet.pdf 

 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards 

Vikas Jathar  

Intel Customer Support – Engineering 

(Under Contract to Intel)
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