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Hello,
Is there any design example available which shows APB master & APB slave or AHB master & AHB slave interface in platform designer.
Edit component instantiation option where i can change the description of interface. So than it will also affect RTL code of that IP.
Please clarify these doubts
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Hi,
Only can find design example for AXI.
Gitlab:
Refer to the attached file.
Documents and design resources links (search for keyword AXI):
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-examples-overview.html (Intel® FPGA Design Examples)
https://rocketboards.org/foswiki/Documentation/WebHome (RocketBoards)
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?s=Newest&q=axi (design store)
https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/interface-signal-types.html (Platform Designer)
Course training and video:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html
https://www.youtube.com/watch?v=LdD2B1x-5vo&t=1s
Best Regards
Sheng
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These web links are useful for cyclone 10 gx development board.
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Hi,
Let me know if you have any further updates or concerns.
Best Regards
Sheng
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Hi,
Is there any design example related to cypress superspeed EZ-USB FX3 connection with cyclone 10 gx intel fpga. The connection with cypress and cyclone 10 gx using interconnection board diagram.
Please help me to solve this issues.
Thank you,
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Hi,
I found one in design store but using Cyclone IV.
Thanks,
Best Regards
Sheng
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Hi,
Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.
Thank you.
Best Regards,
Sheng
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