disfunctional jtag uart below clock crossing bridge in QSYS

[Altera_Forum]

Hi, 

 I have a NIOS2 and an Avalon JTAG UART together in a QSYSsystem which have an intervening Avalon clock crossing bridge inbetween them. When the NIOS2 reads from the JTAG UART it locks up. This design meets timimg in all of the temperature domains, and the QSYS interconnect to me looks very ordinary with one side of the clock crossing bridge running at full rate DDR clock and the other side on the one-half rate DDR clock.  I do see the following warning which is probably a hint at the cause, but determining what might be done to fix this situation in such a high level tool as QSYS is somewhat problematic. Any suggestions are appreciated!   I am using Quartus 12.1 (I attempted to install the 12.1 service pack, but after the install quartus help indicates that no service pack is installed).  Warning (15400): WYSIWYG primitive "xxxxxxxx:xxxxxxxxInstance|xxxxxxxx_periph:periph|xxxxxxxx_periph_jtag_uart_gdb:jtag_uart_gdb|timedDataSys_periph_jtag_uart_gdb_scfifo_w:the_timedDataSys_periph_jtag_uart_gdb_scfifo_w|scfifo:wfifo|scfifo_4991:auto_generated|a_dpfifo_bf91:dpfifo|dpram_2jf1:FIFOram|altsyncram_5v22:altsyncram1|ram_block2a1" has a port clk0 that is stuck at GND  Thanks!