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Altera_Forum
Honored Contributor I
761 Views

afi_half_clock of DDR3 SDRAM Controller with UniPHY

Hi, 

 

While configuring DDR3 controller GUI, I forgot to check "enable half rate clock option". Still I was able to connect other component's clock with afi_half_clk in Qsys. Qsys did not generate any error for this. The design also went through synthesis and PAR with out any error.  

 

When I tried to download my elf on to the FPGA, I got an error saying could not download elf and not much information about the source of the error. And debugging this took some time.  

 

Had Qsys reported an error, it would have been easy to fix it. Is there any reason why Qsys ignored this error? 

 

Thanks
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Altera_Forum
Honored Contributor I
30 Views

Thanks for reporting this issue! It is probably also the cause of the confusion reported in this thread! 

 

http://www.alteraforum.com/forum/showthread.php?t=39609
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