dsp builder-quartus project

[Altera_Forum]

hello, 

 i have created a project for multichannel duc, and able to generate quartus project file. the top module is   entity duc is  port (  channel : in std_logic_vector(7 downto 0);  data : in std_logic_vector(15 downto 0);  valid : in std_logic_vector(0 downto 0);  duc_i : out std_logic_vector(15 downto 0);  duc_q : out std_logic_vector(15 downto 0);  ochhannel : out std_logic_vector(7 downto 0);  ovalid : out std_logic_vector(0 downto 0);  busin_d : in std_logic_vector(31 downto 0);  busin_a : in std_logic_vector(15 downto 0);  busin_w : in std_logic_vector(0 downto 0);  busout_v : out std_logic_vector(0 downto 0);  busout_r : out std_logic_vector(31 downto 0);  clk : in std_logic;  areset : in std_logic;  h_areset : in std_logic  ); end;  can anyone tell me about those 3 signals... what is the significant of those signals... how do we provide those signals as input from outside?  regards  nandak

[Altera_Forum]

If you want a processor to update your coefficients then this bus is generated(data, address, write...). If you don't want update then set your filter block to constant coeffs and the bus will disappear. 

 By the way channel input is not needed ! as it is not connected internally as far as I know.

[Altera_Forum]

--- Quote Start ---  If you want a processor to update your coefficients then this bus is generated(data, address, write...). If you don't want update then set your filter block to constant coeffs and the bus will disappear.  By the way channel input is not needed ! as it is not connected internally as far as I know.  --- Quote End ---    hello,  i changed the read/write mode into constant, for all the filters and NCO. but still it is showing the same in NCO entity...   component working_duc_nco is  port (  busin_d : in std_logic_vector(31 downto 0);   busin_a : in std_logic_vector(15 downto 0);  busin_w : in std_logic_vector(0 downto 0);  xin_c : in std_logic_vector(7 downto 0);  xin_v : in std_logic_vector(0 downto 0);  xin_p_0 : in std_logic_vector(23 downto 0);  xin_p_1 : in std_logic_vector(23 downto 0);  xin_p_2 : in std_logic_vector(23 downto 0);  xin_s_0 : in std_logic_vector(0 downto 0);  xin_s_1 : in std_logic_vector(0 downto 0);  xin_s_2 : in std_logic_vector(0 downto 0);  sinout_0 : out std_logic_vector(17 downto 0);  sinout_1 : out std_logic_vector(17 downto 0);  sinout_2 : out std_logic_vector(17 downto 0);  cosout_0 : out std_logic_vector(17 downto 0);  cosout_1 : out std_logic_vector(17 downto 0);  cosout_2 : out std_logic_vector(17 downto 0);  ncoout_v : out std_logic_vector(0 downto 0);  ncoout_c : out std_logic_vector(7 downto 0);  clk : in std_logic;  areset : in std_logic;  h_areset : in std_logic  );  end component;  what change should i have to make ?

[Altera_Forum]

If it is fixed frequency then I don't want the tool to generate processor interface. If it does set interface inputs to zero and ignore its outputs

[Altera_Forum]

hello, 

thanks for your reply... actually my nco frequencies are constant. can you elaborate more??? regards nandak

[Altera_Forum]

--- Quote Start ---  hello, thanks for your reply... actually my nco frequencies are constant. can you elaborate more??? regards nandak  --- Quote End ---    at port map use the following connections: busin_d => x"00000000", -- processor data   busin_a => x"0000", -- processor address  busin_w => "0", -- processor write  regarding phase you ca also set it to a constant e.g. zeros.  as such the nco should use the constant value entered at gui block level. in case it does not (and i doubt it) then set above data to your constant, address to base address and write to "1"

[Altera_Forum]

hello kaz, 

 actually i want to update my nco frequencies. how do we use it with those address and data lines? what kind of interface will be using for that, like AXI anything?  regards  nandak