dynamic configuration issue of fpll from arria 10

[lambert_yu]

Hi, all

   quartus ip : quartus 191

   IP : fpll

  operation mode : fraction mode

  For change the frequency of fpll:

  I modify c0/m/n/k, after configure these register , then use register to reset and re-calibrate fpll.

  I found that:(during simulation)

  1) if there's no m change, though k value is changed, the fpll could not synthesis the new frequency;

    workaround : I must change m to another value then change it back, then update k value; the fpll could synthesis the new frequency; I don't know why. it's so strange.

 2) Though there's workaround solution, but I found that sometimes, previous and current  k value has large difference(for example ,previous value is 32'h98dbc000 , current value is 32'h5b110000), but the fpll could not provide correct frequency. How could I resolve this issue? Or which way will I  need to try?

Best Regards,

Lambert

[lambert_yu]

I made sure I have written all register correctly through reading the related register after write. And I found  that 1st k value, 2ed k value has same frequency; 3rd value, 4th value has another same frequency; 1st and 2ed k value is diff; 3rd value and 4th value is diff. Update frequency is 861us.

[JohnT_Intel]

Hi,

Have you try to use the latest Quartus to see if the issue is still observed? Is this only happen in simulation or it is also observed in hardware?

[lambert_yu]

Hi,

   Now I only have tried the quartus 191 and only did the simulation,  I will check this IP using quaruts 24.

[lambert_yu]

I tried quartus 242, and I met the same issue.

[JohnT_Intel]

Hi,

Please share the step to duplicate the issue.

[lambert_yu]

Hi,

   Just because I could not send our project to you(I have limited authority). I could only present my implementation step.

   1. Configure fpll to one default frequency;

    2. During simulation, use fixed M count, and continue to adjust K count. (gap about 800 us).

         Use same N and C0 count;

        For the dynamic configuration: 

        1. configure C0;

         2. configure M

         3, configure N;

          4. configure K

          5. power down to do reset and re-calibration

     Or maybe could you help provide one example, and I could try it at my side, thanks

Best Regards

[lambert_yu]

And I found that when I use the quartus 242 to re-generate or re-design the fpll, the simulation model all belongs to quartus 191, why?

  fpga type: arria 10 10ax115n2f45e1sg.

[JohnT_Intel]

Hi,

Have you re-generate the IP? Can you share with me the design?

[lambert_yu]

Hi,

   I am so sorry that I have limited authority that I could not transfer our design to you. But for the fpll design, I could provide the related configuration :

And I think this information could help to generate the related IP. About dynamic logic, maybe you need to re-design.

[JohnT_Intel]

Hi,

When you generate the design, the IP should have regenerated. Can you confirm if there is new folder or file created based on the latest Quartus?