eSPI Agent Core, Virtual Wire PLT_RST#

[WFitt]

Hi,

We are about to use the Intel eSPI Agent Core in a FPGA on our mainboard for communication with an Intel Elkhart  Lake CPU module.

Actually we need the virtual wire PLT_RST# as a main reset on our mainboard . But unfortunately this signal is not led out of the IP core.

Is there a recommended workaround to get another reset from CPU to our mainboard via eSPI?

Is it planned in a next version of eSPI Agent Core to lead the virtual wire PLT_RST# out of the core as a virtual wire port like the other virtual wires?

Regards 

Wolf

[Farabi]

Hello,

Do you have the board userguide link etc. so we can refer to the correct board? Is this FPGA board from Intel PSG(Programmable Solution Group) ?

regards,

Farabi

[WFitt]

Hi Farabi,

It is a mainboard developed by our company. On this board there are connectors for a CPU module and a FPGA for communication with the Intel Atom CPU.

Until now we are using a CPU module with Intel Baytrail processor communicating with FPGA via LPC bus.

Now we are going to use our new Elkhart Lake CPU module communicating via eSPI with the FPGA. 

Actually we need the PLT_RST# from eSPI as a main reset on our mainboard. To this my above questions are referring.

Regards

Wolfram

[Farabi]

Hello,

I am sorry, we need more clarification on what problem do you have related to FPGA?

This forum is for supporting FPGA issues.

regards,

Farabi

[WFitt]

Hi,

I think it is a FPGA issue. 

My questions again:

We are using the Intel eSPI Agent Core in an Intel FPGA.

We need the eSPI virtual wire PLT_RST# as a main reset on our mainboard . The virtual wire PLT_RST#  is used internally by the eSPI Agent core. Unfortunately this signal is not led out of the IP core as port.

1. Is there a recommended solution for getting out a reset output signal from the IP core?

2. Is it planned in a next version of eSPI Agent Core to lead the virtual wire PLT_RST# out of the core as a virtual wire port like the other virtual wires?

Regards

Wolfram

[Farabi]

Hello,

I am escalating this request to engineering to fix this. Please give me sometime to get the solution for this issue.

regards,

Farabi

[Farabi]

Hello,

Sorry to keep you waiting. There is feedback from engineering on this request, I will give the details later.

regards,

Farabi

[Farabi]

Hello, 

Feedback from Engineering, we have tested with MAX10 and Arria 10. Both can see the pltreset_n virtual wire at the output port. 

MAX10 we tried on Quartus 18.1. 

Arria 10 we tried on Quartus 22.3.

When generating the IP, you need to select virtual wire channel or all chanels like below:

below is the screen shot from virtual wire index table, taken from Embedded peripheral IP userguide, eSPI chapter. The direction is Host to Agent(output). The peripheral channel allows you to communicate between the eSPI host and the
eSPI endpoints located at the agent side (example: PORT80). To reset the channel, use the platform reset (PLTRST_n Virtual Wire).

After compilation, you will see the "pltrst_n" output port from eSPI LPC bridge IP. 

Below is RTL viewer for Arria 10: 

and below is RTL viewer for MAX10:

There is limitation you need to consider on the clock ratio :

regards,
Farabi

[WFitt]

Hi Farabi,

thank you for your response.

Unfortunately your answer is relating to eSPI LPC Bridge. We are using eSPI Agent Core. A pltrst_n port is not existing at this.

Regards

Wolfram

[Farabi]

Hello Wolfram,

Feedback from engineering: they are aware of this issue.

Fix plan : the lptrst_n virtual wire port will be available in next Quartus release.

bug fix tracking (internal only) : https://hsdes.intel.com/appstore/article/#/15012503647

regards,

Farabi

[Farabi]

Hello,

Engineering suggested if you can use the espi_reset_n port available in the current IP which having same function as RESET# port of eSPI agent IP.

regards,

Farabi

[Farabi]

Hello,

Do you have further question on this case?

regards,

Farabi