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when i managed to use signal compiler to convert fir.mdl to vhdl and failed to create fir.vhdl.i got the error:Entity fir -> block x16: Input pin(1) is not connected to an Altera Block. I was hoping some one could help me!
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I had got the problem too, but in my design, it was a warning. how to solve it?
What do you have inside your .mdl? Is it simply one instance of FIR compiler? Perhaps you can post your .mdl here so we can help look at it...
