I am bringing up communication between stratix iv fpga and ddr2 sdram. For that I have instantiated DDR2 SDRAM Controller with UNIFY using Quartus prime standard edition 16.0.
I want to simulate the example project first to understand various signal and according to document "https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ddr_ddr2_sdram_hp.pdf" , I am supposed to get testbench/<>_example_top_tb.v and memory_model.v files.
But they are not there in generated files.
Am I missing something in the instantiation or UNIFY doesn't come with above files?
Any suggestion in this regard is very helpful.
As what I remember, for this old device, after you click on the generation, it will pop-up a window to ask you either want to generate the example design, you have to tick the option to generate example design then click ok. It only will generate the testbench file for you.
Hi, Now I understand the reason. Since you are using UniPHY, so the document that you referring is incorrect. the document that you are using now is ALTMEMPHY which is obsolete.
The IP that you instantiate in the QII 16.0 is UniPHY which include in this document:
For uniphy, after you generate the IP with example design, it will create a folder <variable>_example_design
You may refer to the uniphy documentation as above on how to use the design.