help about EPCS

[Altera_Forum]

I want to know what is the difference between Active Serial Memory Interface and EPCS Serial Flash Controller

[Altera_Forum]

This is how I got it, but I'm not totally sure, if it's right. Please anybody tell us, if something is wrong. 

 In "former" times ASMI was used as interface between FPGA and a configuration device including appropriate commands. Now it seems with the ASMI the pure signalpaths ASDI, nCS, DCLK and DATA is meant.   For more information about ASMI check out: http://www.altera.com/literature/lit-cyc2.jsp -> Application Notes -> AN 379: Active Serial Memory Interface Controller Reference Design (dated March 2005!) or search the altera.com page for "Active Serial Memory Interface Data Sheet" (dated May 2003!)   The EPCS Serial Flash Controller is a Device Controller which can be included in a SOPC Builder system to connect to an EPCS Serial Configuration Device.  For more information on the EPCS Serial Configuration Device check out: http://www.altera.com/literature/lit-config.jsp -> Configuration Handbook, Volume 2, Section I. FPGA Configuration Devices, Chapter 4. Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet   For more information on the EPCS Device Controller Core check out: http://www.altera.com/literature/quartus2/lit-qts-peripherals.jsp -> Quartus II Handbook Volume 5: Embedded Peripherals, Section I. Memory Peripherals, Chapter 3 EPCS Device Controller Core   If you use an EPCS with a Nios II processor system you find: "For Nios II processor users, the EPCS controller core supersedes the Active Serial Memory Interface (ASMI) device. New designs should use the EPCS controller instead of the ASMI core" (page 3-1 of Quartus II Handbook Volume 5: Embedded Peripherals, Section I. Memory Peripherals, Chapter 3 EPCS Device Controller Core)  Hopefully this helped. Did it answer your question?

[Altera_Forum]

A 'quick' / 'simple' difference between ASMI and the SOPC interface is that ASMI was used PRIOR to the SOPC 'component' to allow a designer to use the excess EEPROM locations of the EPCS device for 'non-volatile' storage. Usually with a NiosII core processor. 

 Mike

[Altera_Forum]

thank you, this is a very useful help.