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Altera_Forum
Honored Contributor I
1,163 Views

help on Design guidelines for data transfer from DE2-115 to PC

Hello everyone, 

 

I am a beginner in the field of FPGA and I am currently working my way through a lot of information.  

As part of project, I need to transfer data from a FPGA board DE2-115 to a PC. More precisely, we already have an independent verilog module that works and produces data bits and we would like to transmit these bits as fast as possible to a PC, where a server application write the data in a text file and save it. 

 

I know that there are multiple options to handle the transmission of data using for instance Triple Speed Ethernet IP-cores in conjunction with Nios2 some people seems to make TSE work without using an RTOS. I was also wondering if it was possible to realize my project without using a NioS and just IP-cores. 

 

I would like to have the simplest design that guarantees the best level of performance. But at this point I do not really know which direction I should take. 

 

Thank you for your help and comments!
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8 Replies
Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

 

I am a beginner in the field of FPGA and I am currently working my way through a lot of information.  

 

--- Quote End ---  

You've come to the right place then. There are lots of people who will help you on this forum. 

 

 

--- Quote Start ---  

 

As part of project, I need to transfer data from a FPGA board DE2-115 to a PC. More precisely, we already have an independent verilog module that works and produces data bits and we would like to transmit these bits as fast as possible to a PC, where a server application write the data in a text file and save it. 

 

--- Quote End ---  

Are these bits always produced, or can you deal with data in blocks? 

 

For example, there is memory on the board, could you stream the bits 'as fast as possible' to the RAM, and then read it out slower? 

 

How 'fast' do you need the results? Your speed will likely be limited by the transfer speed off the board. 

 

 

--- Quote Start ---  

 

I would like to have the simplest design that guarantees the best level of performance. But at this point I do not really know which direction I should take. 

 

--- Quote End ---  

There are several options; 

 

1) Use one of the NIOS processor examples which contains an ethernet IP core and server code, eg., simple socket server. 

 

2) Use the JTAG interface. This is the slowest, but could be the easiest. 

 

3) The DE2 boards have a USB interface. There might be some IP cores to use that for communications with the host. Google indicates that the example DE2_NIOS_DEVICE_LED shows how to implement a USB connection to the host (I have not looked at this example, its probably a USB HID, so no driver needed on the host). 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
67 Views

Hey Dave, 

 

Thank you so much for your help!  

 

To answer some of your comments: 

1) the bit are always produced. Treating as block would be possible, I think, but at this point this is just data bits. Ideally I would like the streamed bits to be routed directly to the Ethernet Link without using a RAM module (that I think require to assemble the bit into binary words compatible with the RAM modules). 

 

2) I would like to send the bit at something like 100 Mbit/s (eventually more) or at the maximum speed (or close to) that the board can offer. 

 

What would you recommend to interface my verilog module with a Nios 2-based system? 

 

Thank you again for your help and your quick answer! 

Cheers.
Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

 

1) the bit are always produced. Treating as block would be possible, I think, but at this point this is just data bits. Ideally I would like the streamed bits to be routed directly to the Ethernet Link without using a RAM module (that I think require to assemble the bit into binary words compatible with the RAM modules). 

 

--- Quote End ---  

 

 

There really is no 1-bit data transport. You will need to pack the data into a larger packet. For example, you could create a block of samples that is the payload to a UDP packet. You might want to use some of the payload for a header indicating the start bit number and the length, and then you'd wrap that in a standard UDP packet 

 

http://en.wikipedia.org/wiki/user_datagram_protocol 

 

There is a UDP offload example on the Altera Wiki: 

 

http://www.alterawiki.com/wiki/nios_ii_udp_offload_example 

 

Perhaps someone who has used these examples can comment on whether they would be suitable for your application. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
67 Views

Thank you again Dave, I will have a look to those reference. 

 

I have read a lot about the DE2-115 and from Altera handbooks recently but the learning curve is pretty steep.  

 

Still based on the project I would like to do I have another question (and I am sure many more in a near future :o) ).  

 

I have seen that to make the connection work with the host PC, it is necessary to have a C code to be run by the NiOS 2. My question is: if I have my Verilog module which generates data bits continuously and that I need to assemble them. Should I perform this operation via a piece of code in C or should it be described in Verilog? It is not clear to me what is performed at the hardware level and at the software level. 

 

Also Is it a piece of C code that need to be used to root the bits from my module to the MAC controller ? or is it something described at the Hardware level? 

 

Thanks again for the help. 

Cheers, 

 

Pdoc
Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

 

Still based on the project I would like to do I have another question (and I am sure many more in a near future :o) ).  

 

--- Quote End ---  

Feel free to ask questions! 

 

 

--- Quote Start ---  

 

I have seen that to make the connection work with the host PC, it is necessary to have a C code to be run by the NiOS 2. My question is: if I have my Verilog module which generates data bits continuously and that I need to assemble them. Should I perform this operation via a piece of code in C or should it be described in Verilog? It is not clear to me what is performed at the hardware level and at the software level. 

 

--- Quote End ---  

The hardware will always be able to perform more operations per clock cycle than software, so you want to use the hardware to create blocks of data that software can then handle.  

 

For example, lets say you decide you want to send data in 4kB blocks to your processing logic. Your logic that generates a bit per clock cycle can pack bits into bytes, and then write those bytes into a memory block. When the 4kB packet is ready, it can interrupt the processor. The hardware can then write to a different 4kB memory. The processor than has 4k clocks to remove the data from the memory before the hardware needs it again. The processor interrupt service routine can be used to schedule a task which creates a UDP packet, and then copies (via DMA) the 4kB payload your logic just created. As you work with the design, you may find you can optimize, by creating the UDP packet 'in place'. Once the UDP packet is ready, it can be given to the TSE interface to be transported. 

 

Since you are just beginning, my advice is to attach the problem one small piece at a time. 

 

1) Get your bit generation logic working. 

 

2) Create some simple NIOS II projects and understand how to write code, use the IDE, and handle interrupts. 

 

3) Write some UDP code on a Linux machine or Windows machine. Send data between two machines. 

 

4) Look at the NIOS II UDP examples, simple socket server examples, etc. Once you understand them, modify them. 

 

5) Once you understand all the pieces, then assemble them into the system described above. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
67 Views

Dear Dave, 

 

thank you again for the advice ! 

I had step 1) working already and I am in the middle of point 2) (in fact I was working with point 2) for a couple of days already :o)  

 

The thing that I need to figure out, indeed, is how to handle the interrupts ! 

 

Thank for the guidelines. This really give me a good structure to tackle the problem. 

 

Cheers, 

Pdoc.
Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

 

The thing that I need to figure out, indeed, is how to handle the interrupts! 

 

--- Quote End ---  

 

 

Here's a document that shows how I attack this type of problem: 

 

http://www.ovro.caltech.edu/~dwh/ucos/project_ar1803.pdf 

 

Its for an ARM processor using GCC. You can use the same technique to understand the low-level of the NIOS processor. In general, you can handle interrupts two ways; write the assembler hooks as I show in this document, or use compiler attributes or pragmas.  

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
67 Views

Thanks again Dave for your help and the link to the documents! 

Cheers, 

Pdoc.
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