how to design ip core?

[Altera_Forum]

I am a green hand. I need capture cmos camera data with FPGA. With IO methed to capure can't satisfy real-time. So,I want to design a IP core include FIFO and DMA. But I don't know how to start. Can someone tell me the particular design flow.Some example is great! 

I'm a fresh man here,and this my first question. Thank you very much!

[Altera_Forum]

Have a look at the Avalon spocification. If you can format your data into an Avalon Stream, then you can use the already existing FIFO and SGDMA cores in SOPC builder. 

Avalon specification: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf SOPC Builder component design walkthrough: http://www.altera.com/literature/hb/qts/qts_qii54007.pdf