Re: implement ram with logic blocks

Altera_Forum · ‎01-10-2012

Hi all!

I am designing an Avalon-MM interface with a page system: a page register is used as address of a memory and a data register is used to read/write the memory.

The memory I instanciate is an altsyncram.

For functional purpose I need a true dual port memory (1 port for Avalon-MM, 1 port for core processing).

    channel_dst_mac_addr_ram : altsyncram
    generic map
    (
        lpm_type                    => "altsyncram",
        intended_device_family      => "Stratix IV",
        power_up_uninitialized      => "TRUE",
        operation_mode              => "BIDIR_DUAL_PORT",
        outdata_reg_a               => "CLOCK0",
        clock_enable_input_a        => "BYPASS",
        address_reg_b               => "CLOCK0",
        indata_reg_b                => "CLOCK0",
        wrcontrol_wraddress_reg_b   => "CLOCK0",
        outdata_reg_b               => "CLOCK0",
        clock_enable_input_b        => "BYPASS",
        numwords_a                  => NB_PAGES,
        numwords_b                  => NB_PAGES,
        widthad_a                   => pos_log2(NB_PAGES),
        widthad_b                   => pos_log2(NB_PAGES),
        width_a                     => 48,
        width_b                     => 48
    )
    port map
    (
        clock0                      => ast_clk,
        address_a                   => channel_dst_mac_addr_ram_address_a,
        wren_a                      => channel_dst_mac_addr_ram_wren_a,
        data_a                      => channel_dst_mac_addr_ram_data_a,
        q_a                         => channel_dst_mac_addr_ram_q_a,
        address_b                   => channel_dst_mac_addr_ram_address_b,
        wren_b                      => channel_dst_mac_addr_ram_wren_b,
        data_b                      => channel_dst_mac_addr_ram_data_b,
        q_b                         => channel_dst_mac_addr_ram_q_b
    );

My problem is that the number of pages I need (i.e. the memory depth) is usually quite low, like 2 or 3, but Quartus uses M9K to implement that memory.

Is there an option to force the altsyncram to be implemented in logic blocks rather than in onchip RAMs, that I can turn on when NB_PGE is low?

The system is for Stratix IV, I use Quartus 10.1.

Thx

Altera_Forum · ‎01-10-2012

I think you must set the ram_block_type parameter to "MLAB"

Altera_Forum · ‎01-10-2012

adding lpm_hint => "RAM_BLOCK_TYPE=MLAB", in the generic map should force use of the smaller 640-bit sized MLAB memory blocks

Altera_Forum · ‎01-10-2012

Quartus usually picks whetever is available. Is there any reason you specifically dont want an M9K? If there are plenty spare, whats the problem?

Quartus should automatically pick MLABs if the M9Ks are getting a bit scarce.

Altera_Forum · ‎01-10-2012

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Quartus usually picks whetever is available. Is there any reason you specifically dont want an M9K? If there are plenty spare, whats the problem?

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There is never enough memory inside the chosen FPGA! :)

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Quartus should automatically pick MLABs if the M9Ks are getting a bit scarce.

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This is not true! QII sometimes messes things up quite badly. I've seen it build a large memory with M4k and then using a M144k for a small fifo (Quartus II 9.1sp2 - Stratix II GX). I had to go through all my code and add the appropriate lpm_hint parameter to get the project fitted.

Altera_Forum · ‎01-10-2012

Agreed!!

We are desperatly in need of memory and can't afford to waste M9K like this :(

MLAB would be better than M9K, but my question was: is it even possible to force implementation with logic elements?

I think there is an option like this for FIFOs:


Parameter     use_eab
Type          String
Required      No
Description   Specifies whether or not the FIFO megafunction is 
              constructed using the RAM blocks. The values are ON or 
              OFF.
              Setting this parameter value to OFF yields the FIFO 
              megafunction implemented in logic elements regardless of 
              the type of the TriMatrix memory block type assigned to the 
              ram_block_type parameter.

Thx

Julien

Altera_Forum · ‎01-10-2012

Indeed, I should have copied a bit more from my code:

use_eab => "OFF",

will force usage of LE-registers to build the memory block

Altera_Forum · ‎01-10-2012

Since you said you only need 2 or 3 addresses, I'd build my own component using 2 or 3 48bit register arrays and a simple decoder.

This would involve some coding, but it is likely to ensure a minimal resource implementation.

Altera_Forum · ‎01-11-2012

@Cris72: actually I said 'usually 2 or 3 addresses', but sometimes I can go up to several thousands. So I'll stick to the altsyncram.

@josyb: so does use_eab => "OFF" works for altsyncrams?

Altera_Forum · ‎01-12-2012

up: so does use_eab => "OFF" works for altsyncrams?

Altera_Forum · ‎01-12-2012

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up: so does use_eab => "OFF" works for altsyncrams?

--- Quote End ---

I did use it once for a dcfifo, but I checked the help (QII 9.1sp2 and QII 11.1sp1) for altsyncram and there the parameter seems to be "IMPLEMENT_IN_LES" which you want to set to "ON". Why don't you try this?

Altera_Forum · ‎01-12-2012

Cool!!

I have listed all the parameters of the altsyncram core in order to understand everything, and I could not figure out what that one meant.

So now 1) I figured out what it is 2) it might solve my issue!!

Thanks!

I'll test that right now, and tell if it works

Julien