hi, everyone!
I am new to FPGA and NIOS
I was trying to capture frame from the vip test pattern generator and write to sdram using SGDMA. But the data came from the test pattern generator was 24bit(R G B) and SGDMA only support 8bit 16 bit 32bit and 64bit. So I tried to convert the RGB data to RGB0 by simply put extra 8bit 00000000.
I wrote something like those in verilog and created my component:
assign data_out = {data_in,8b'0};
assign ready_out=ready_in;
assign valid_out=valid_in;
assign sop_out=sop_in;
assign eop_out=eop_in;
It seemed that I lost 8 bits data(which I am not sure. It coult R or B, since the data I read from the sdram was like 0x xxxx0000)
I was wondering how could it happened and what I suppose to do.Like how can write the verilog or what can I do to convert the avalon streaming width from 24bit to 32bit. I am just newbie, it will be very nice that some of you can give some advice.
I wish all of you have a nice day ! :)
