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DChau5
Novice
538 Views

mSGDMA: Streaming to MM problem

Hi everyone,

 

Recently, I want to play with mSGDMA and learn about it so just make up my own project to test and see the behaviour and know how to control the mSGDMA. However, I got stuck and have tried everything I know but still cannot fix it.

 

HARDWARE:

-HPS with h2f_lw_bridge

-mSGDMA:

  • Streaming to Memory Mapped
  • Data width: 8
  • Data Path FIFO depth: 32
  • Descriptor FIFO depth: 32
  • Maximum transfer length: 1KB
  • Transfer type: Aligned Accesses
  • Everything else is disabled

-My customized counter with streaming interface: I made this component just to test the mSGDMA. The counter increase the value every 1 second and output it in streaming interface. It has:

  • Data width: 8 bits
  • Data bits per symbol: 8 bits

-LED PIO: written by mSGDMA write master with the transfered data and it is supposed to increase every second.

 

SOFTWARE:

Here is C code:

typedef struct sgdma_descr { uint32_t *read_addr; uint32_t *write_addr; uint32_t length; uint32_t control; }sgdma_descr_t;   int main () { uint32_t status ; /*bridge configuration*/ alt_bridge_init(ALT_BRIDGE_LWH2F,NULL,NULL); alt_bridge_init(ALT_BRIDGE_H2F,NULL,NULL);   sgdma_descr_t descr; sgdma_descr_t *descr_ptr = &descr;   // configure the descriptor for ST to MM transferring descr->read_addr = NULL; descr->write_addr = 0; // address of PIO seen by mSGDMA write master descr->length = 1; descr->control =(1<<31) ; // no setting, just go for one data transfer   // feed the descriptor to the descriptor slave alt_write_word(DESCR_RADDR,descr->read_addr); alt_write_word(DESCR_WADDR,descr->write_addr); alt_write_word(DESCR_LENGTH,descr->length); alt_write_word(DESCR_CONTROL,descr->control);   uint32_t status; while(1) { // observe value inside the registers status = alt_read_word(CSR_STATUS); printf("Status: %u\n",status);   status = alt_read_word(CSR_CONTROL); printf("CONTROL: %u\n",status);   status = alt_read_word(CSR_LEVEL); printf("LEVEL: %u\n",status);   } return 0; }

It states that the mSGDMA is still busy transfering ( Busy bit is set ) and the descriptor buffer is empty ( Descriptor buffer empty bit is set and the value in Write fill level register is 0 ). However, I see nothing is transferred because the LEDs are not lighted up.

 

I had tried the same test with regular DMA Controller and it worked fine. But with mSGDMA it does not work with my test.

 

Hope someone can give me a hint how to fix this. Thanks in advance !

 

Cheers!

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4 Replies
GuaBin_N_Intel
Employee
136 Views

Your command sequence seems good to initiate a DMA transfer. Can you confirm whether streaming data is written correctly into the SGDMA? You may use SignalTap or simulation to check it.

DChau5
Novice
136 Views

Hi GNg,

 

Thanks for your response!

 

I also doubt that my streaming interface is a problem because I work fine with MM-MM. I did check it my streaming interface with Modelsim and also implemented it with Avalon FIFO, it works fine.

 

Maybe I will test it with SignalTap but I need to learn how to use because I have never used it before 😅 .

 

One thing also got my attention. At first, my counter's data width is 32 bits and data bits per symbol = 32. I got a warning that the mSGDMA data bits per symbol is only 8, if I want to transfer 32 bits data, I have to configure it to 8 bits data per symbol and 4 symbol per beat. I do not know how to change it to 4 symbol per beat. Whenever I change to 8 data bits per symbol ( with data width is 32 ) in "New Component" configuration window, it only transfer my 8 LSB data[7:0].

 

Once again, thanks for your answer. I will check on SignalTap when I have time.

GuaBin_N_Intel
Employee
136 Views

It is pretty straightforward for SignalTap usage. Go through this training https://www.youtube.com/watch?v=DCUhsezqydQ would help. Which interface do you need to change its bits per symbol? source streaming from counter? Refer to avalon-mm spec https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf, Table 18,pg43, you are able to change its streaming properties using "dataBitsPerSymbol"

AKb
Beginner
122 Views

Hi,

 

 

I am trying to implement triple speed ethernet in Cyclone 10 FPGA. I have integrated triple speed ethernet core in platform designer in qsys. If i pump data and do loop back in system side of MAC, its working fine. I am able to monitor Start of packet, data valid, data, End of packet properly in signal tap. Now my aim is that i try to capture the streaming data in system side of MAC directly in Nios side memory. For this i am using Modular Scatter gather DMA. For receive data i am using one MSGDMA in streaming to memory mode and one for transmit data i am using one MSGDMA in  memory to streaming mode. I try to capture data in descriptor memory in onchip ram. But i am not getting any data.

I have doubt about my connections of MSGDMA in Qsys.There are no any specific examples detailing how to use MSGDMA with TSE. Some people have done it with SGDMA . I am using quartus 18.1. So how to go about it. How to capture data in onchip RAM.

 

Kindly guide

 

Av