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megacore fft 8.0 problem

Altera_Forum
Honored Contributor II
959 Views

Hi everyone, 

 

i face a strange problem with megacore fft. 

The operation mode i used is 

burst mode, Quad output, 1024 points, 2 engines 

and the device is Cyclone II 

Quartus II v80sp1 

 

i have do a lots of testing for the fft megacore... 

 

first, i would like to read data from fifos which also the megacore produce from the wizard to be the fft inputs (include the real part and image part). 

 

i write control module (in Verilog) to handle the control signals between fifos and fft. 

 

in my design, the fft only accept one frame(1024 data samples) one time, so i need to use burst mode. i read user guide of FFT Megacore Function and understand that there is a small fifo buffer at the sink of the block. 

i write finite state machine to control sink_sop, sink_eop, sink_valid carefully, and watch the simulation result. 

it goes wrong! 

 

when the sink_ready is asserted, i asserted rdreq(fifo read enable signal) to read data from fifo, and then asserted sink_valid. 

sink_sop asserted only at the first data, sink_eop asserted only at the last data, and sink_valid asserted from sink_sop to sink_eop. 

there is no any source_error occurs in the process, but the source_real and source_image are wrong. :((the source_sop, source_eop and source_valid are OK, source_ready is asserted) <= the source_real and source_image come out, but the value is incorrect.  

 

more information i got, when i remove fifos and control module. only the fft megacore, and input the sink data from simulation(Vector waveform file). it works correctly!!! Why?:confused: 

 

anyone can do me a favor, please~ 

 

ps. attach files are the simulation results
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2 Replies
Altera_Forum
Honored Contributor II
100 Views

Hi taylor, 

 

Can you tell me the clock you're using??
Altera_Forum
Honored Contributor II
100 Views

Hello again, 

 

i'm having some problems with FFT megacore, because source_sop is never asserted and sink_ready is asserted just for a few clock's and then comes to low. 

 

i'm using a 30ns clock. 

 

I attach my simulator waveforms. 

 

Thanks.
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