FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5946 Discussions

mem_reset_n always is low from DDR3 hard controller

EBoln
New Contributor I
945 Views

Hi,

i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk

EBoln_0-1629963652340.png

What else can affect this signal?

0 Kudos
16 Replies
AdzimZM_Intel
Employee
923 Views

Hi Sir,

 

I'm Adzim. Thanks for using Intel Community.

 

According to the KDB here, it's looks like the global and soft resets can only trigger the mem_reset_n signal.

 

Are you using the example design in your simulation?

If not, can you simulate your IP with the example design?

 

Which Quartus software that you used?

 

Regards,

Adzim

EBoln
New Contributor I
920 Views
I am using 18.1.1 and 20.1 standard edition
AdzimZM_Intel
Employee
908 Views

Have you try to simulate your IP with the example design in your simulation?

EBoln
New Contributor I
905 Views

At the moment, no, since there were no problems when using the core on Cyclone 5

AdzimZM_Intel
Employee
903 Views

Can you give it a test?

 

So before this you're working on Cyclone V device and it's worked.

But now you try to implemented it in Arria V is it?

Do you create a new IP for the Arria V or you use the existing project?

EBoln
New Contributor I
899 Views

I copy qsys file with DDR3 controller from CycloneV project to ArriaV project, ofcourse i change FPGA type in qsys file

EBoln
New Contributor I
899 Views

And i try create new qsys with controller

AdzimZM_Intel
Employee
891 Views

Thanks for clarifying about your project.

I guess there is no error during the IP generating process and compilation.

 

But since you're facing some issue with the Arria V device, can you use the example design to simulate your IP in the Arria V?

EBoln
New Contributor I
881 Views

I try to simulate... and all signals correct

EBoln_0-1630307660170.png

 

AdzimZM_Intel
Employee
838 Views

Great!

 

Can you check the connection between your IP and your design?

And compare it with the example design.

EBoln
New Contributor I
837 Views

I create new project with same qsys file with ddr3 controller

EBoln
New Contributor I
801 Views

I changed the core type to soft controller and keep track of mem_reset_n generation. 

EBoln_0-1630413564653.pngEBoln_1-1630413643146.png

dataout[0] from ARRIAV_DDIO_OUT - mem_reset_n

pll_addr_cmd_clk - exist

DATAINHI and DATAINLO - 2'b11

ARESET - 1'b0(from ~reset_reg[14])

Why???

AdzimZM_Intel
Employee
713 Views

Hi sir,


The signal tap tool cannot be used to get the signal from the mem_reset_n because the signal is the conduit between the memory and phy.

The signal tap can get the signal between user design and the memory controller.


In order to see the signal, you can do it by the simulation tool such Modelsim.

By simulation your design in the tool, you can trace the waveform of your signal.

By right you can see the interaction of the mem_reset_n signal.


Regards,

Adzim


AdzimZM_Intel
Employee
621 Views

Hi sir,


I hope you're doing great.


Do you still have further question on this case?


Regards,

Adzim


EBoln
New Contributor I
616 Views
AdzimZM_Intel
Employee
615 Views

Setting the case to closure.


Reply