FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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multiport Ethernet reference design

Honored Contributor II

I can't find a reference design to show me how to connect a shared fifo to the triple speed Ethernet IP if i set it in multiport mode. Does anyone have a build that uses the multiport configuration with the shared fifo? 


Also may I know if I can connect two sgmii signals from 2 FPGAs together( FPGA1_rx to FPGA2_tx and vice versa) without a phy inbetween? Any special requirements for these to work? I presume you could have loopbacked on the SGMII interface before so could work but not sure.
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