hi, I am dealing with ip core clocked video(CVI) in and clocked video out(CVO).And there is a pin named overflow on CVI, and a pin named underflow on CVO, my question is when an overflow or underflow happens, does it output high or low, thanks for reply!
In my opinion, the meaning of all signals is clearly stated in the IP user guide. Generally, a logic signal not clearly marked as negated (like e.g. n_reset) can be expected active high.
The pins are active high (high when overflow/underflow occurs).The CVI will overflow if data is it's internal FIFO fills up before it has a chance to send it's data to downstream components. The CVO will underflow if it is outputting data and it's internal FIFO becomes empty because the upstream components were not able to supply it quickly enough. Jake
I experience active low overflow and underflow pins on cyclone iii board. Verified by adding an leds to the overflow and underflow pins. When overflow the pin connected to the LED goes off.
Did you probe the underflow overflow pins on the Cyclone III board? If I remember this correctly, the output leds on the Cyclone III board are active low, so they should go OFF when they receive a HIGH signal. The leds light up when they receive a LOW signal creating the voltage difference needed between the anode cathode so that the current can flow.I'm also experiencing CVO underflow in a design, just recently I posted a new thread, probable it's related to timing or bandwidth issues..not quite sure yet
Yes I connected the underflow and overflow pins to the LEDs to test the activity. I guess you are the right the LEDs are active low, I had checked them earlier.I also have the severe CVO underflow problems, I have checked previous threads about bandwidth without sucess. I also tried to use pipeline and buffer the output into external memory before sending it to CVO, all I get is flickering output. I had a chance to meet with Altera Engineers in a conference recently and they told me the problem could be that I am trying to apply 2d filtering on 3 planes using one filter but the planes are in series, and also the size of my image 1920x1080 is too big to be processed with cyclone iii. with the maximum ddr2 memory controller speed at 166 Mhz. The interesting thing is that there exists a video design from altera where all the processing and sampling has been implemented without any pipelining and I think that design must have worked although I could not test it. And I could not get a simple DVI input output running without pipelining and using external FIFOs. If you get any success do let me know?