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Altera_Forum
Honored Contributor I
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problem with reed salomon simulation quartus 13.1

i'm trying to simulate this core, but i have a problem 

when i driven a correct codeword to reed salamon ip decoder (attach jpg file) everthing is ok, 0 numerr and so on without fail signal asserted 

when i just replace 1 symbol i got fail signal assert + numer = 16. how it could be possible? 

 

i attached also my core configuration.
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Altera_Forum
Honored Contributor I
14 Views

another thing is. 

i generate also the encoder core and when i put the pattern  

 

0x01 0x02 0x03 0x4.........0x8d 

 

i got the correct 32 bytes of parity. 

 

0x6d 0x8d 0x89 0x21 0x88 0x4d 0x6b 0x210x2e 0x3c 0xd6 0x8e 0x68 0x54 0x72 0x31 0x52 0xbd 0x9e 0xf7 0x45 0xf5 0x70 0x20 0x60 0xc4 0xe2 0xec 0x0b 0xef 0x18 0x1a 

 

when i use the decoder core with the pattern 

 

 

 

0x01 0x02 0x03 0x3.........0xd8 0x6d 0x8d 0x89 0x21 0x88 0x4d 0x6b 0x210x2e 0x3c 0xd6 0x8e 0x68 0x54 0x72 0x31 0x52 0xbd 0x9e 0xf7 0x45 0xf5 0x70 0x20 0x60 0xc4 0xe2 0xec 0x0b 0xef 0x18 0x1a 

 

with 1 wrong symbol i got  

 

number of error : 16 with defail signal asserted 

 

someone can help please? 

 

thanks 

 

 

--- Quote Start ---  

i'm trying to simulate this core, but i have a problem 

when i driven a correct codeword to reed salamon ip decoder (attach jpg file) everthing is ok, 0 numerr and so on without fail signal asserted 

when i just replace 1 symbol i got fail signal assert + numer = 16. how it could be possible? 

 

i attached also my core configuration. 

--- Quote End ---  

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