FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6561 Discussions

qsys avalon stream arbiter

Altera_Forum
Honored Contributor II
‎07-25-2018 12:44 PM
1,681 Views

I need module which has 2 Avalon-St sinks (data in) and single Avalon-St source (data out) and simply redirects one of the sink to source. Is there an option to make qsys infer arbitration logic and connect source0 streams from st_pipeline_stage_1/2 to sink0 stream in st_pipeline_stage_0? When I try to connect the second wire the first connection disappears.

Preview file
21 KB
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎07-25-2018 06:23 PM
928 Views

Just add a streaming mux. It's a standard component in the IP Catalog (Avalon-ST Multiplexer Intel FPGA IP). What kind of arbitration are you looking for?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.