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ref_clk in IP compiler for PCI Express

Altera_Forum
Honored Contributor II
1,034 Views

Please help me, 

I am planning to use IP compiler for PCI Express Mega function to create my PCIE hard IP, in that whether i can use a PLL generated (using megafunction) 125MHz ref_clk or i need to use a direct clock from FPGA pin. I am having an input clock of 200MHz, so i am planning to use PLL to generate 125MHz or 100MHz and give it to clk_ref pin of "IP compiler for PCI Express Mega function" is it correct? 

Regards, 

dil
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1 Reply
Altera_Forum
Honored Contributor II
95 Views

The recomended way is directly feed the refclk pin from FPGA pin. For PCIe core, the refclk should directly source from refclk of PCIe edge connector.

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