I'm simulating the s10 pcie avmm core in the bridge mode, gen3 x4, 256-bit avmm data bus. From the RP model, I sent a 64-byte write request and then a 64-byte read request at the same address.
From the EP side, I can see that the rxm bar4 interface is working fine. It sent out the write request and received correct data (bot readdata and readdatavalid signals were correct). But it seems the pcie core never sent back the read data back to the RP.
From the waveform, altera_pcie_s10_hip_ast_pipen1b_inst/rx_st_* signals were toggling correctly, but altera_pcie_s10_hip_ast_pipen1b_inst/tx_st_* never toggled after rxm_bar4_readdatavalid was asserted. These signals are drived from the encrypted model "dcore" and I cannot dig further.
Please help. I'm stuck here. Many thanks.
I have just tested it by using Quartus v20.1, I've generated the PCIe gen3x4 example design, and then run the simulation in ModelSim SE, everything works fine, and I can see the rx_st* as well as tx_st* signals are toggling. I would suggest you to use the examples design to run the simulation if you haven't done so.