set_input_delay / set_output_delay -min query

[Knug]

I currently have a query wrt set_input_delay / set_output_delay -min (wrt hold)  :

My example below :

#**************************************************************
# Create Clock
#**************************************************************

set PERIOD_CLK 100.000

create_clock -name {clk} -period $PERIOD_CLK -waveform { 0.000 50.000 } [get_ports {in_clk}]

#****************************************************
# Create the associated virtual input clock
#****************************************************
create_clock -name {clk_virt} -period $PERIOD_CLK -waveform { 0.000 50.000 }

#**************************************************************
# Set Output Delay
#**************************************************************
# output_max = [expr $Td_max + $Tsu]
# Tsu is the Max setup time of the external device
# Td_max is the max trace delay of dataout to the external device
set output_max 70.0

# output_min = [expr $Td_min - $Th]
# Th is the Min hold time of the external device
# Td_min is the min trace delay of dataout to the external device
set output_min 50.0

set_output_delay -clock clk_virt \
-max $output_max \
[get_ports flash_nce]

set_output_delay -clock clk_virt \
-min $output_min \
[get_ports flash_nce]

Noticed in many -min input/output delay constraints they use negative values instead of positive ones. Negative values does that mean the hold time after the rising edge of the clock?

I also noticed people using +ve values (see my example above, output_min = +50). With an output_min = -3.0 I had eg flash_addr[5] hold time violations reported worse case -0.569nS (Fast Model)

My understanding is that:  output_min = [expr $Td_min - $Th] can be positive or negative depending on the Td_min & Th values.  As long as I have the output_min value less than the output_max value, that should be ok. I'm I right to say this ?  

Please comment here.

Regards,

Kevin

[sstrell]

In your equations, you're missing the clock skew, the difference between the clocks arriving at the FPGA and the downstream (output) device.  So the equations should be (given that you know that downstream device's Tsu and Th):

output max = data trace (max) - clock skew (min) + Tsu

output min = data trace (min) - clock skew (max) - Th

It's OK if the min value is negative.

[Knug]

Hi @sstrell 

I only shown few constrains in my original message. I also constrained the following which was flagged as unconstrained. 

#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -setup -rise_from clk -rise_to clk 0.2
set_clock_uncertainty -hold -rise_from clk -rise_to clk 0.2

set_clock_uncertainty -setup -rise_from clk_virt -rise_to clk 0.2
set_clock_uncertainty -hold -rise_from clk_virt -rise_to clk 0.2

set_clock_uncertainty -setup -rise_from clk -fall_to clk 0.2
set_clock_uncertainty -hold -rise_from clk -fall_to clk 0.2

set_clock_uncertainty -setup -rise_from clk -rise_to clk_virt 0.2
set_clock_uncertainty -hold -rise_from clk -rise_to clk_virt 0.2

#Determine internal clock uncertainties
derive_clock_uncertainty

[Knug]

Hi @sstrell 

>> output min = data trace (min) - clock skew (max) - Th

Is this right?

Shouldn't it have been :

     output min = data trace (min) - clock skew (max) + Th

[sstrell]

No, it's correct.  You subtract the hold requirement to get the smallest amount possible (-min), even if it's negative.

And clock uncertainty constraints are used to describe the properties for a clock.  They don't constrain a clock directly.

[SyafieqS]

Hi Kevin,

Any update on this?