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Hi everyone,
I'm using DSP blocks to implement my design. simulation with simulink was successful but when I want to simulate with Modelsim I always have no outputs. when I compile with signal compiler the compilation is successful too. Is anyone have any idea about the cause of this problem; and is there a way to transform the input files from simulink (.mat files) to .vw files in order to try simulating with quartus IILink Copied
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