the compatibility issue about the PCIe IP for Cyclone V and Cyclone IV

[csy]

HI,

I am using EP4CGX50CF23I7N to design a new board with ARM + FPGA structure. And i need a pcie port on it.

As shown, EP4CGX50CF23I7N should be classified into Cyclone IV GX Series.

From Platform Designer in Quartus 18.1, we know that we should use 'IP Compiler for PCI Express' as the starting point and re-use it into my app.

Based on some unavoidable reasons, I only have a Cyclone V board to be used. (The board is designed by terasic, and detailed is listed at http://www.terasic.com.cn/cgi-bin/page/archive.pl?Language=China&CategoryNo=182&No=1158&PartNo=4)
If i use cyclone v to be the starting point of my design, i should use 'Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP' to be the first step. And then keep on desiging my app.

I have three questions.

1. What about the diff between the two IP cores?

2. If I decide to start my design based on Cyclone IV. How about the difficulty when I migrating to Cyclone IV.

3. Even the listed IP core corresponding to two different user guide docs. At least from the viewpoint of apps,I think it is no so much difference between them. How about your evaluation?

[SengKok_L_Intel]

Hi

1. The IP is targeted for different devices, and you need to double-check if the data rate and link width that you plan to do is supported in both devices.
2. If both devices use the AVMM interface, it should be straightforward for you to port over your application design from CV to CIV.
3. Yes, as per the PCIe spec, both are similar.

Regards -SK

[SengKok_L_Intel]

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