timing_error_for_pll_afi_clock_on_ddr3_ip_controller

[SERMASWATHIKA]

Hi Team,

  I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces.

pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board.

 Nios processor also connected with afi clock only (200 Mhz)

For this design , i am getting pll_afi_clock setup time violation.

i have attached the timing report. 

PLease give solution for this.

[SERMASWATHIKA]

Hi,

  the critical path which you are showing is currently not available as i have added one pll to manage the clocks for other rtl logic.

 Now the worst slack is reduced and logic level is 4 only.still timing violations are there.

it is showing within ip files. How can i add pipeline register here in this logics?

[SERMASWATHIKA]

Hi,

 the critical path which you are showed in response is removed from timing violation as i added pll for managing clocks for rtl logic.

Now some other timing violations are there

these violations are within ddr3 library files. How to add pipeline register in this path? 

[SERMASWATHIKA]

Hi,

  Thanks for your response.

  I just modified the qsys design for better timing performance so instead of ddr_pll clock , added pll ip to drive other rtl logic clock.

  With that timing is improved. But still path has violation

The logic level is 4 only. These are listed for ddr3 ip library files. How to add pipeline register here?

[TingJiangT_Intel]

I see, can you share the modified project with me？

Just choose the same option as the previous one is fine.

[SERMASWATHIKA]

Hi,

  I have attached the modified project archive. PLease check this and for every compilation timing is varying.

[TingJiangT_Intel]

Hi there, could you please share the ziped design with me, as we need to do some test with it which can't be compiled with only QAR file,

[SERMASWATHIKA]

hi ,

i have added the zip file, please check and help me to resolve this issue.

[Kenny_Tan]

Just look into the screenshot that you provide, when I try to compile the design and load the PD, I see that you left your avalon pipeline bridge as dangling.

Any reason for that? You can actually connect this pipeline from your CPU.data master to Avalon_pipeline_bridge to TC timing to increase the pipeline for you to close the timing. I would suggest you download one of the example design in the NIOS II in the design store to see how the connection look like.

As you can see above, there are quite a lot of red module that prevent me to make modification of your design for timing closure. Can you let me know what are the setting that you use or the _hw.tcl script location for your custom module?

[Kenny_Tan]

Attached screenshot here

[SERMASWATHIKA]

Hi Ken,

  unexpectedly that mm_bridge master connection is removed. actually it will connect to custom rtl avalonport. That part i have connected.

hw.tcl file is located in rtl directory and i have generated from ipx command only .

for ddr , i will create another thread seperately.

But i do have timing violation for pll div clk .

so please look into this also.

[Kenny_Tan]

Hi Sermaswathika,

What I means is your mm_bridge master need to be connected in order to have a better timing. You may take a look into this design example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tightly-coupled-mem.html , it show how the pipeline bridge was connected from NIOS II to the periheral subsystem. You may need to do the same as well.

I do not see the rtl directory that you have in the zip files, can you send it to us?

My reported failure is different than yours,

Can you download the design example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tightly-coupled-mem.html and make sure the connection and module comparable compare to your design. After making the changes, zip the design with the RTL directory and send it back to us to review. 

Thanks,

Best regards,
Kenny Tan

[SERMASWATHIKA]

Hi Ken,

Thanks for sharing the reference. I have implemented the pipeline bridge for other peripherals and ethernet separately. Still timing violation is there.

I could not be able to zip all files as it takes large memory size and i cannot attach in this forum. 

i have attached the archive project which size is acceptable in this forum.

[Kenny_Tan]

Besides, this timing violation on the Platform designer, you also have violation on the DDR itself.

Can you create a separate thread to resolve this timing violation for the DDR part? As this will require tuning the DDR setting in your design. thanks

[TingJiangT_Intel]

Hi there could you share you design with me via email, I'll send a email to you. Thanks

[TingJiangT_Intel]

Hi there, is there any updates on this issue?

[SERMASWATHIKA]

Hi,

i have checked the design with clk connected from inclk directly and compiled the design.

But still timing violations are there.

i have created another threat for ddr3_timing and sharing project archive with reports.

based on the inputs from that thread, modified the project .

Sharing the project with this

[TingJiangT_Intel]

Hi there, I tried to open your project, but Timing Analyzer can't be opened which can't show me your violations.

And there are also errors exist in the platform designer. So please look into this and if the project is too huge you can share it with me via previous email.

Thanks

[TingJiangT_Intel]

Hi there, any updates on this? If you have sent a email please let me now in case I miss it.

[SERMASWATHIKA]

hi

i can not share my design in mail as it will not allow to share

[TingJiangT_Intel]

Hi there, I see. If so, we are unable to help modify and do test on your design.

What we can help is giving some general advice according to your timing analyzer reports.

Thanks.