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Hi,
the critical path which you are showing is currently not available as i have added one pll to manage the clocks for other rtl logic.
Now the worst slack is reduced and logic level is 4 only.still timing violations are there.
it is showing within ip files. How can i add pipeline register here in this logics?
Hi,
the critical path which you are showed in response is removed from timing violation as i added pll for managing clocks for rtl logic.
Now some other timing violations are there
these violations are within ddr3 library files. How to add pipeline register in this path?
Hi,
Thanks for your response.
I just modified the qsys design for better timing performance so instead of ddr_pll clock , added pll ip to drive other rtl logic clock.
With that timing is improved. But still path has violation
The logic level is 4 only. These are listed for ddr3 ip library files. How to add pipeline register here?
Just look into the screenshot that you provide, when I try to compile the design and load the PD, I see that you left your avalon pipeline bridge as dangling.
Any reason for that? You can actually connect this pipeline from your CPU.data master to Avalon_pipeline_bridge to TC timing to increase the pipeline for you to close the timing. I would suggest you download one of the example design in the NIOS II in the design store to see how the connection look like.
As you can see above, there are quite a lot of red module that prevent me to make modification of your design for timing closure. Can you let me know what are the setting that you use or the _hw.tcl script location for your custom module?
Attached screenshot here
Hi Ken,
unexpectedly that mm_bridge master connection is removed. actually it will connect to custom rtl avalonport. That part i have connected.
hw.tcl file is located in rtl directory and i have generated from ipx command only .
for ddr , i will create another thread seperately.
But i do have timing violation for pll div clk .
so please look into this also.
Hi Sermaswathika,
What I means is your mm_bridge master need to be connected in order to have a better timing. You may take a look into this design example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tightly-coupled-mem.html , it show how the pipeline bridge was connected from NIOS II to the periheral subsystem. You may need to do the same as well.
I do not see the rtl directory that you have in the zip files, can you send it to us?
My reported failure is different than yours,
Can you download the design example https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tightly-coupled-mem.html and make sure the connection and module comparable compare to your design. After making the changes, zip the design with the RTL directory and send it back to us to review.
Thanks,
Best regards,
Kenny Tan
Besides, this timing violation on the Platform designer, you also have violation on the DDR itself.
Can you create a separate thread to resolve this timing violation for the DDR part? As this will require tuning the DDR setting in your design. thanks
