FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

transiver using the internal PLL insted of ref clock

Altera_Forum
Honored Contributor I
756 Views

Hi  

 

I've currently trying to implement an 10g transiver on my dev board. I've used the megaWizard to build me a Altera Determistic transceiver and I've connected and mapped all the signals correctly with pin numbers etc.  

 

However i have a problem with the external reference clock, and thus want to use the interal ALTPLL to drive the reference clock on the transceiver. I've read the documentation on the ref_clk input to the transceiver and it shoult be possible, but when i try i get build errors saying its not possible.  

 

So Is this possible or not and if so how do i connect it becuase i cannot just connect the output of the interal pll to the input pin (ref_clk).  

 

Regards  

Anders
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
76 Views

 

--- Quote Start ---  

Hi  

 

However i have a problem with the external reference clock, and thus want to use the interal ALTPLL to drive the reference clock on the transceiver. I've read the documentation on the ref_clk input to the transceiver and it shoult be possible, but when i try i get build errors saying its not possible.  

 

So Is this possible or not and if so how do i connect it becuase i cannot just connect the output of the interal pll to the input pin (ref_clk).  

 

Regards  

Anders 

--- Quote End ---  

 

 

Hi, 

What is your development board? and what is the clock frequency you want from the board? I am using a Transceiver Signal Integrity board, Stratix IV GT. My experience about reference clock is that there are several clock generators on board that provide ref clk for transceiver channel with a specific frequency. Depend on your clk frequency, you assign to a corresponding clock generator PIN on the board. So, you should to refer to the board reference manual for more detail. The msg saying that it is not possible maybe because your frequency is not supported by the generator.
Altera_Forum
Honored Contributor I
76 Views

 

--- Quote Start ---  

Hi, 

What is your development board? and what is the clock frequency you want from the board? I am using a Transceiver Signal Integrity board, Stratix IV GT. My experience about reference clock is that there are several clock generators on board that provide ref clk for transceiver channel with a specific frequency. Depend on your clk frequency, you assign to a corresponding clock generator PIN on the board. So, you should to refer to the board reference manual for more detail. The msg saying that it is not possible maybe because your frequency is not supported by the generator. 

--- Quote End ---  

 

 

 

I have the same board although its with a Stratix V. however it is as rameshrai points out "Not simple enough", and i'm developing to a system where, if it is possible, i can leave thoes clock generators out. Simple design, simple PCB routing.  

 

Regards Anders
Reply