FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

DDR3 Native to Avalon-MM conversion

Dsp Builder - create NCO or ReesSolomon vhdl and matlab files bit exact

Adavnced SEU Detection

PASR (Partial Array Self-Refresh) for LPDDR2

works in testbench, but not on the board [IP UART TX and RX]

V-Series Avalon-MM DMA Interface for PCIe Solutions

88E1111 Marvell PHY Chip Clock

10G ETHERNET MAC IP -10GBase-R Design example

time limited sof not generated when using Frame Buffer II IP

TSE doesn't have data on RGMII output, functional simulation works fine (Max 10)

VIP Suite - Mixer II background layer

Altera_fp_functions

Design Use 24bit AUDIO CODEC on kit DE1

Quartus 15 ALTLVDS_RX MegaWizard Errors

Altera LVDS serdes IP

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

Unable to simulate DDR3 controller

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)