using JESD204B example design for Arria 10 (using RTL State Machine Control Unit version) with AD9250 ADC.

[EArth1]

 I am getting confused using the JESD204B example design for Arria 10 (using RTL State Machine Control Unit version) with the AD9250 ADC and will really appreciate some help.

I read from the JESD204B IP Core Design Example User Guide (v17.0) page 9 table 4 that the JESD204B supports only some specific parameters for Arria 10. Eg. data rates (6144) and subclass for Arria 10 (subclass 1). The ADC I am using (AD9250 can only go up to 5Gbps. Does it mean I cannot use Arria 10 with this ADC? It is not very clear as to whether this is a limitation of the example design generation or the IP itself. I don’t get any errors when I compile but I am worried it may just revert back to what those default values are and not work with my ADC.

Are the examples designs generated dependent on the parameters you select for the ip? for example, if I specify a data rate of 5000, subclass 1 in the IP generation tab, will the example design generated reflect this including the PLL parameters? or it just give you a fixed set of parameters no matter what you select and you will therefore have to go into the generated files to make those changes ? What are parameters of the example design set to if that is the case?

Even though it says in the same documentation that the IP supports only supports subclass 1 for Arria 10, and I selected same in the ip generation when I go into the configuration file for setting up the ADC, it is clearly setting the ADC up for subclass 0 as can be seen from this line in the ADC.mif file :

22 :  10000000000000000111001100001111; -- AD9250 #1, write 0x0F to parameter subclass/Np register 0x73 for subclass 0   (should be 0x2f if it was to be subclass 1) also there is no register write to enable the ADC to use sysref which is necessary for subclass 1.

I can change these but I am just wondering if there are other things which may also not be set up to parameters I choose in the IP generation. Do I need to edit the PLLs for example? The example design doesn’t give you the .qsys file so I can’t check and edit it via the GUI if they are not set right. I guess I have to edit these parameters manually in the generated IP files? Is there a way I can view these via the Gui without the .qsys file?

[Nathan_R_Intel]

​Hie,

Please check my replies(in bold)  to your questions:

I read from the JESD204B IP Core Design Example User Guide (v17.0) page 9 table 4 that the JESD204B supports only some specific parameters for Arria 10. Eg. data rates (6144) and subclass for Arria 10 (subclass 1). The ADC I am using (AD9250 can only go up to 5Gbps. Does it mean I cannot use Arria 10 with this ADC? It is not very clear as to whether this is a limitation of the example design generation or the IP itself. I don’t get any errors when I compile but I am worried it may just revert back to what those default values are and not work with my ADC.

The limitation is on the example design generation and not the IP.  The parameter limitation is on the L,M,F parameters and not on the data rate. Arria 10 supports up till 6.144Gbps, hence you can use 5Gbps. Anyway there is a rule check to avoid example design generation for parameter configuration not supported. If you enter a non supported parameter configuration, the Generate Example Design tabs will be grayed out. Hence, if you are able to generate the Example Design itself, it will be based on values entered and not default values. Hence, 5Gbps is supported by Arria 10.

Are the examples designs generated dependent on the parameters you select for the ip? Yes

for example, if I specify a data rate of 5000, subclass 1 in the IP generation tab, will the example design generated reflect this including the PLL parameters?  Yes it will

You door it just give you a fixed set of parameters no matter what you select and you will therefore have to go into the generated files to make those changes ?  You don't need to make any manual changes on the generated files. Please use the JESD204B FPGA Intel IP GUI to select your data rate and other parameters such as LMF.

What are parameters of the example design set to if that is the case?  None you need to select manually as explained above.

Even though it says in the same documentation that the IP supports only supports subclass 1 for Arria 10, and I selected same in the ip generation when I go into the configuration file for setting up the ADC, it is clearly setting the ADC up for subclass 0 as can be seen from this line in the ADC.mif file :

22 :  10000000000000000111001100001111; -- AD9250 #1, write 0x0F to parameter subclass/Np register 0x73 for subclass 0  (should be 0x2f if it was to be subclass 1) also there is no register write to enable the ADC to use sysref which is necessary for subclass 1.

I can change these but I am just wondering if there are other things which may also not be set up to parameters I choose in the IP generation. Do I need to edit the PLLs for example? The example design doesn’t give you the .qsys file so I can’t check and edit it via the GUI if they are not set right. I guess I have to edit these parameters manually in the generated IP files? Is there a way I can view these via the Gui without the .qsys file?

As described in our documentation, only subclass 1 is supported.  Hence, we don't recommend or support editing the parameters manually.

Regards,

Nathan

[EArth1]

       Hi Nathan,

  Thank you for the info. It has help me make some progress but not quite there yet.

Now I am able to get lane0 to initialise but never lane 1. that is rx_pcs_data_valid0 goes high and I get the ‘K’ initialisation characters 0xBC. rx_pcs_data_valid1 never goes high so the core is unable to send the sync signal.

Any ideas why this may be so?

These are the commands I use to initialise the ADC.

# #AD9250 simple config to subclass 0,scrambling enabled

master_write_32 $m 0x4 0x005F15; #2, write 0x15 to link control 1 register 0x5F to disable the lane

master_write_32 $m 0x4 0x006E81; #2, write 0x81 to parameter SCR/L register 0x6E to enable scrambler

master_write_32 $m 0x4 0x00701F; #2, write 0x1F to parameter K register 0x70 for K=32

master_write_32 $m 0x4 0x005E22; #2, write 0x22 to quick config register 0x5E for L=2, M=2

master_write_32 $m 0x4 0x00730F; #2, address 0x73xx (0x2F to parameter for subclass 1(0x0F for subclass 0)

master_write_32 $m 0x4 0x00FF01; #2, write 0x01 to device update register 0xFF to update the settings     

master_write_32 $m 0x4 0x005F14; #2, write 0x14 to link control 1 register 0x5F to enable the lane

Am I missing anything?

It seems like somehow I only enable lane 0.

any help will be deeply appreciated