using emif ip amm interface

[CosmoKramer]

Hello,

We are using quartus 23.4 and  seeing discrepancy in the polarity of ctrl_amm signal on the emif ip between documentation and the example design. 

As per simulation of the example design - read/write request is accepted by the ip only when ctrl_amm is high. But user guide is saying the opposite. 

https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/ctrl-amm-for-ddr4.html

Could someone please clarify what does a high and low on ctrl_amm mean?

How can we know that our request has been accepted by the ip?

[AdzimZM_Intel]

Hello,

Which ctrl_amm signal that you mean? Can you provide the screenshot as well? Thanks.

Maybe you can check in the example design top level file to see if the signal has been negated.

Regards,

Adzim

[CosmoKramer]

Hello, 

I mean the amm_ready signall in the ctrl_amm inerface mentioned in the section  4.1.1.15 of this document - ug-ag-emi-683216-780962.pdf

Here is the link - https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/ctrl-amm-for-ddr4.html

code for emif_controller.v in the ip folder:

output wire   amm_ready_0,   //  ctrl_amm_0.waitrequest_n,                   Wait-request is asserted when controller is busy

code for emif_controller.v  in the example design:

output wire          amm_ready_0,               // ctrl_amm_0.waitrequest_n,           Wait-request is asserted when controller is busy

the comment and user guide are conflicting. 

Please let me know which one is correct and what is that correct polarity?

thank you. 

[sstrell]

I've been confused by this as well.  "ready" is not a signal in Avalon, but waitrequest is and it's normally active high, though you can use it as active low according to the spec, though I haven't seen any IP use it in this way (probably only used when someone creates a custom component/IP).

So if the EMIF IP user guide calls the signal "ready" and it's called that in the code but then the comment in the code says the signal is "waitrequest_n" implying the bus is paused when this signal is low, they kind of jive with each other, though it is still confusing. 

So the signal coded as "ready" means that when it's high, "waitrequest_n" is high so the bus is active and not paused.  When "ready" is low, "waitrequest_n" is low and since it is active low, the bus is paused.

Very odd.

[matferronato]

I've also raised this issue in one of the replies in this topic. I believe this is an oversight on the documentation side. Maybe it should be flagged to be patched in the next revision.

[AdzimZM_Intel]

Hello,

The amm_ready signal from the EMIF IP module is an active low signal.

The controller is busy when this signal is low.

The description may a bit confusing.

I will try to raise this concern to improve in the UG.

Regards,

Adzim

[AdzimZM_Intel]

Hello,

Since there is no further question in this thread and currently the concern has been raised to the engineering, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards,

Adzim